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Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should

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print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-22 19:12:43 +00:00
parent e7cf062537
commit 597fa65373
4 changed files with 24 additions and 3 deletions
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13
lib/Target/ARM/ARMInstrThumb.td
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@ -721,6 +721,19 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
let Inst{7-0} = addr; let Inst{7-0} = addr;
} }
// FIXME: Remove this entry when the above ldr.n workaround is fixed.
// For disassembly use only.
def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
"ldr", "\t$Rt, $addr",
[/* disassembly only */]>,
T1Encoding<{0,1,0,0,1,?}> {
// A6.2 & A8.6.59
bits<3> Rt;
bits<8> addr;
let Inst{10-8} = Rt;
let Inst{7-0} = addr;
}
// A8.6.194 & A8.6.192 // A8.6.194 & A8.6.192
defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
t_addrmode_is4, AddrModeT1_4, t_addrmode_is4, AddrModeT1_4,

6
test/MC/Disassembler/ARM/thumb-printf.txt
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@ -7,17 +7,17 @@
# CHECK-NEXT: add r3, sp, #20 # CHECK-NEXT: add r3, sp, #20
# CHECK-NEXT: ldr r5, [r3], #4 # CHECK-NEXT: ldr r5, [r3], #4
# CHECK-NEXT: str r3, [sp] # CHECK-NEXT: str r3, [sp]
# CHECK-NEXT: ldr.n r3, #52 # CHECK-NEXT: ldr r3, #52
# CHECK-NEXT: add r3, pc # CHECK-NEXT: add r3, pc
# CHECK-NEXT: ldr r0, [r3] # CHECK-NEXT: ldr r0, [r3]
# CHECK-NEXT: ldr r4, [r0] # CHECK-NEXT: ldr r4, [r0]
# CHECK-NEXT: ldr.n r0, #48 # CHECK-NEXT: ldr r0, #48
# CHECK-NEXT: add r0, pc # CHECK-NEXT: add r0, pc
# CHECK-NEXT: ldr r0, [r0] # CHECK-NEXT: ldr r0, [r0]
# CHECK-NEXT: ldr r0, [r0] # CHECK-NEXT: ldr r0, [r0]
# CHECK-NEXT: blx #191548 # CHECK-NEXT: blx #191548
# CHECK-NEXT: cbnz r0, #6 # CHECK-NEXT: cbnz r0, #6
# CHECK-NEXT: ldr.n r1, #40 # CHECK-NEXT: ldr r1, #40
# CHECK-NEXT: add r1, pc # CHECK-NEXT: add r1, pc
# CHECK-NEXT: ldr r1, [r1] # CHECK-NEXT: ldr r1, [r1]
# CHECK-NEXT: b #0 # CHECK-NEXT: b #0

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -30,6 +30,9 @@
# CHECK: ldmia r0!, {r1} # CHECK: ldmia r0!, {r1}
0x02 0xc8 0x02 0xc8
# CHECK: ldr r5, #432
0x6c 0x4d
# CHECK: str r0, [r3] # CHECK: str r0, [r3]
0x18 0x60 0x18 0x60

5
utils/TableGen/ARMDecoderEmitter.cpp
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@ -1652,6 +1652,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12")
return false; return false;
// FIXME: Use ldr.n to work around a Darwin assembler bug.
// Introduce a workaround with tLDRpciDIS opcode.
if (Name == "tLDRpci")
return false;
// Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST. // Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST.
if (Name == "t2LDRDpci") if (Name == "t2LDRDpci")
return false; return false;