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BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-21 18:56:31 +00:00
parent 7bf7a446a5
commit 5a18ebc70c
1 changed files with 13 additions and 2 deletions
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15
lib/Target/ARM/ARMInstrInfo.cpp
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@ -298,6 +298,11 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
return NewMIs[0];
}
static bool isPredicated(MachineInstr *MI) {
MachineOperand *PMO = MI->findFirstPredOperand();
return PMO && PMO->getImmedValue() != ARMCC::AL;
}
// Branch analysis.
bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
@ -312,7 +317,8 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
if (I == MBB.begin() ||
isPredicated(--I) || !isTerminatorInstr(I->getOpcode())) {
if (LastOpc == ARM::B || LastOpc == ARM::tB) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false;
@ -331,7 +337,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() &&
isTerminatorInstr((--I)->getOpcode()))
!isPredicated(--I) && isTerminatorInstr(I->getOpcode()))
return true;
// If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
@ -407,6 +413,11 @@ bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
switch (MBB.back().getOpcode()) {
case ARM::BX_RET: // Return.
case ARM::LDM_RET:
case ARM::tBX_RET:
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::B:
case ARM::tB: // Uncond branch.
case ARM::tBR_JTr: