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[PowerPC] Basic support for P9 atomic loads and stores
This patch corresponds to review: http://reviews.llvm.org/D18032 This patch provides asm implementation for the following instructions: lwat, ldat, stwat, stdat, ldmx, mcrxrx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic
parent
7a8b700c13
commit
5a73f4bec5
@ -163,6 +163,10 @@ def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
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def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
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"Treat vector data stream cache control instructions as deprecated">;
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def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
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"true",
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"Enable instructions added in ISA 3.0.">;
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/* Since new processors generally contain a superset of features of those that
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came before them, the idea is to make implementations of new processors
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less error prone and easier to read.
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@ -244,12 +244,22 @@ def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
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// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
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def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
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"ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
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let hasExtraDefRegAllocReq = 1 in
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def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
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"ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
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Requires<[IsISA3_0]>;
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}
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let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
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def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
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"stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
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let mayStore = 1, hasSideEffects = 0 in
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def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
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"stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
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Requires<[IsISA3_0]>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
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def TCRETURNdi8 :Pseudo< (outs),
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@ -905,6 +915,10 @@ def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
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"ldux $rD, $addr", IIC_LdStLDUX,
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[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
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NoEncode<"$ea_result">, isPPC64;
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def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
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"ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
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Requires<[IsISA3_0]>;
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}
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}
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@ -800,6 +800,20 @@ class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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let Inst{31} = XT{5};
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}
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// XForm_base_r3xo for instructions such as P9 atomics where we don't want
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// to specify an SDAG pattern for matching.
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class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin>
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: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
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}
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class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin>
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: XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
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let FRA = 0;
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let FRB = 0;
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}
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// XX*-Form (VSX)
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class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -777,6 +777,7 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
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def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
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def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
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def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
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def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
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//===----------------------------------------------------------------------===//
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// PowerPC Multiclass Definitions.
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@ -1574,6 +1575,13 @@ def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
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def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
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"lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
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// The atomic instructions use the destination register as well as the next one
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// or two registers in order (modulo 31).
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let hasExtraSrcRegAllocReq = 1 in
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def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
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"lwat $rD, $rA, $FC", IIC_LdStLoad>,
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Requires<[IsISA3_0]>;
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}
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let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
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@ -1589,6 +1597,11 @@ def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
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"stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
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}
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let mayStore = 1, hasSideEffects = 0 in
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def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
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"stwat $rS, $rA, $FC", IIC_LdStStore>,
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Requires<[IsISA3_0]>;
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let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
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def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
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@ -2359,6 +2372,9 @@ def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
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"mfcr $rT", IIC_SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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} // hasExtraSrcRegAllocReq = 1
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def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
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"mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
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} // hasSideEffects = 0
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// Pseudo instruction to perform FADD in round-to-zero mode.
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@ -104,6 +104,7 @@ void PPCSubtarget::initializeEnvironment() {
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HasHTM = false;
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HasFusion = false;
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HasFloat128 = false;
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IsISA3_0 = false;
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HasPOPCNTD = POPCNTD_Unavailable;
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}
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@ -130,6 +130,7 @@ protected:
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bool HasHTM;
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bool HasFusion;
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bool HasFloat128;
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bool IsISA3_0;
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POPCNTDKind HasPOPCNTD;
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@ -272,6 +273,7 @@ public:
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bool hasHTM() const { return HasHTM; }
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bool hasFusion() const { return HasFusion; }
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bool hasFloat128() const { return HasFloat128; }
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bool isISA3_0() const { return IsISA3_0; }
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POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
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@ -558,3 +558,18 @@ VSX:
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- Load Vector Word & Splat Indexed: lxvwsx
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. Likely needs an intrinsic
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. (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
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Atomic operations (l[dw]at, st[dw]at):
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- Provide custom lowering for common atomic operations to use these
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instructions with the correct Function Code
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- Ensure the operands are in the correct register (i.e. RT+1, RT+2)
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- Provide builtins since not all FC's necessarily have an existing LLVM
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atomic operation
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Load Doubleword Monitored (ldmx):
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- Investigate whether there are any uses for this. It seems to be related to
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Garbage Collection so it isn't likely to be all that useful for most
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languages we deal with.
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Move to CR from XER Extended (mcrxrx):
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- Is there a use for this in LLVM?
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@ -33,6 +33,12 @@
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# CHECK: stdcx. 2, 3, 4
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0x7c 0x43 0x21 0xad
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# CHECK: stwat 2, 3, 28
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0x7c 0x43 0xe5 0x8c
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# CHECK: stdat 2, 3, 28
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0x7c 0x43 0xe5 0xcc
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# CHECK: ptesync
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0x7c 0x40 0x04 0xac
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@ -72,6 +78,12 @@
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# CHECK: ldarx 2, 3, 4, 1
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0x7c 0x43 0x20 0xa9
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# CHECK: lwat 2, 3, 28
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0x7c 0x43 0xe4 0x8c
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# CHECK: ldat 2, 3, 28
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0x7c 0x43 0xe4 0xcc
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# CHECK: sync
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0x7c 0x00 0x04 0xac
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@ -151,6 +151,9 @@
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# CHECK: ldux 2, 3, 4
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0x7c 0x43 0x20 0x6a
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# CHECK: ldmx 2, 3, 4
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0x7c 0x43 0x22 0x6a
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# CHECK: stb 2, 128(4)
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0x98 0x44 0x00 0x80
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@ -658,7 +661,11 @@
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# CHECK: mfocrf 16, 8
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0x7e 0x10 0x80 0x26
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# CHECK: mcrxrx 7
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0x7f 0x80 0x04 0x80
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# CHECK: mtsrin 10, 12
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0x7d 0x40 0x61 0xe4
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# CHECK: mfsrin 10, 12
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0x7d 0x40 0x65 0x26
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@ -73,10 +73,19 @@
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# CHECK-BE: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d]
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# CHECK-LE: stwcx. 2, 3, 4 # encoding: [0x2d,0x21,0x43,0x7c]
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stwcx. 2, 3, 4
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# CHECK-BE: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad]
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# CHECK-LE: stdcx. 2, 3, 4 # encoding: [0xad,0x21,0x43,0x7c]
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stdcx. 2, 3, 4
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# CHECK-BE: stwat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0x8c]
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# CHECK-LE: stwat 2, 3, 28 # encoding: [0x8c,0xe5,0x43,0x7c]
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stwat 2, 3, 28
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# CHECK-BE: stdat 2, 3, 28 # encoding: [0x7c,0x43,0xe5,0xcc]
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# CHECK-LE: stdat 2, 3, 28 # encoding: [0xcc,0xe5,0x43,0x7c]
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stdat 2, 3, 28
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# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
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# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
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sync 2
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@ -131,6 +140,14 @@
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# CHECK-LE: ldarx 2, 3, 4, 1 # encoding: [0xa9,0x20,0x43,0x7c]
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ldarx 2, 3, 4, 1
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# CHECK-BE: lwat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0x8c]
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# CHECK-LE: lwat 2, 3, 28 # encoding: [0x8c,0xe4,0x43,0x7c]
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lwat 2, 3, 28
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# CHECK-BE: ldat 2, 3, 28 # encoding: [0x7c,0x43,0xe4,0xcc]
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# CHECK-LE: ldat 2, 3, 28 # encoding: [0xcc,0xe4,0x43,0x7c]
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ldat 2, 3, 28
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# CHECK-BE: sync # encoding: [0x7c,0x00,0x04,0xac]
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# CHECK-LE: sync # encoding: [0xac,0x04,0x00,0x7c]
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sync
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@ -197,6 +197,9 @@
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# CHECK-BE: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a]
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# CHECK-LE: ldux 2, 3, 4 # encoding: [0x6a,0x20,0x43,0x7c]
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ldux 2, 3, 4
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# CHECK-BE: ldmx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6a]
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# CHECK-LE: ldmx 2, 3, 4 # encoding: [0x6a,0x22,0x43,0x7c]
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ldmx 2, 3, 4
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# Fixed-point store instructions
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@ -833,6 +836,9 @@
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# CHECK-BE: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26]
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# CHECK-LE: mfocrf 16, 8 # encoding: [0x26,0x80,0x10,0x7e]
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mfocrf 16, 8
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# CHECK-BE: mcrxrx 7 # encoding: [0x7f,0x80,0x04,0x80]
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# CHECK-LE: mcrxrx 7 # encoding: [0x80,0x04,0x80,0x7f]
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mcrxrx 7
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# Move to/from segment register
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# CHECK-BE: mtsr 12, 10 # encoding: [0x7d,0x4c,0x01,0xa4]
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