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[InstCombine] use m_APInt to allow demanded bits analysis on splat constants

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294628 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2017-02-09 21:43:06 +00:00
parent 6270090e5c
commit 5a764b03c6
3 changed files with 16 additions and 14 deletions
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23
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -30,18 +30,20 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
assert(I && "No instruction?");
assert(OpNo < I->getNumOperands() && "Operand index too large");
// If the operand is not a constant integer, nothing to do.
ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
if (!OpC) return false;
// The operand must be a constant integer or splat integer.
Value *Op = I->getOperand(OpNo);
const APInt *C;
if (!match(Op, m_APInt(C)))
return false;
// If there are no bits set that aren't demanded, nothing to do.
Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
if ((~Demanded & OpC->getValue()) == 0)
Demanded = Demanded.zextOrTrunc(C->getBitWidth());
if ((~Demanded & *C) == 0)
return false;
// This instruction is producing bits that are not demanded. Shrink the RHS.
Demanded &= OpC->getValue();
I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
Demanded &= *C;
I->setOperand(OpNo, ConstantInt::get(Op->getType(), Demanded));
return true;
}
@ -114,9 +116,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
KnownOne.getBitWidth() == BitWidth &&
"Value *V, DemandedMask, KnownZero and KnownOne "
"must have same BitWidth");
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
// We know all of the bits for a constant!
KnownOne = CI->getValue() & DemandedMask;
const APInt *C;
if (match(V, m_APInt(C))) {
// We know all of the bits for a scalar constant or a splat vector constant!
KnownOne = *C & DemandedMask;
KnownZero = ~KnownOne & DemandedMask;
return nullptr;
}

5
test/Transforms/InstCombine/and.ll
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@ -382,12 +382,11 @@ define i32 @test31(i1 %X) {
ret i32 %A
}
; FIXME: Demanded bit analysis allows us to eliminate the add.
; Demanded bit analysis allows us to eliminate the add.
define <2 x i32> @and_demanded_bits_splat_vec(<2 x i32> %x) {
; CHECK-LABEL: @and_demanded_bits_splat_vec(
; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> %x, <i32 8, i32 8>
; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[Y]], <i32 7, i32 7>
; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
; CHECK-NEXT: ret <2 x i32> [[Z]]
;
%y = add <2 x i32> %x, <i32 8, i32 8>

2
test/Transforms/InstCombine/zext.ll
View File

@ -35,7 +35,7 @@ define <2 x i64> @test3(<2 x i64> %A) {
define <2 x i64> @test4(<2 x i64> %A) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i64> %A, <i64 4294967295, i64 4294967295>
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i64> %A, <i64 63, i64 63>
; CHECK-NEXT: [[XOR:%.*]] = and <2 x i64> [[TMP1]], <i64 23, i64 42>
; CHECK-NEXT: ret <2 x i64> [[XOR]]
;