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[ARM] Add v8.1a "Privileged Access Never" extension
Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235087 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Sukharev
parent
0b86f54604
commit
5ade5fcee4
@ -1420,7 +1420,8 @@ multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
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let isCompare = 1, Defs = [CPSR] in {
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multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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PatFrag opnode, bit Commutable = 0,
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string rrDecoderMethod = ""> {
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def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
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opc, "\t$Rn, $imm",
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[(opnode GPR:$Rn, mod_imm:$imm)]>,
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@ -1448,6 +1449,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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let Inst{15-12} = 0b0000;
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let Inst{11-4} = 0b00000000;
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let Inst{3-0} = Rm;
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let DecoderMethod = rrDecoderMethod;
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let Unpredictable{15-12} = 0b1111;
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}
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@ -4265,6 +4267,30 @@ def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
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def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
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def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
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//===----------------------------------------------------------------------===//
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// ARMv8.1a Privilege Access Never extension
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//
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// SETPAN #imm1
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def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
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"\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
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bits<1> imm;
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let Inst{31-28} = 0b1111;
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let Inst{27-20} = 0b00010001;
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let Inst{19-16} = 0b0000;
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let Inst{15-10} = 0b000000;
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let Inst{9} = imm;
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let Inst{8} = 0b0;
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let Inst{7-4} = 0b0000;
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let Inst{3-0} = 0b0000;
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let Unpredictable{19-16} = 0b1111;
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let Unpredictable{15-10} = 0b111111;
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let Unpredictable{8} = 0b1;
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let Unpredictable{3-0} = 0b1111;
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}
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//===----------------------------------------------------------------------===//
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// Comparison Instructions...
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//
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@ -4369,7 +4395,8 @@ def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
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// Note that TST/TEQ don't set all the same flags that CMP does!
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defm TST : AI1_cmp_irs<0b1000, "tst",
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
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BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
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BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
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"DecodeTSTInstruction">;
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defm TEQ : AI1_cmp_irs<0b1001, "teq",
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
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BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
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@ -4280,6 +4280,23 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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//===----------------------------------------------------------------------===//
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// ARMv8.1 Privilege Access Never extension
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//
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// SETPAN #imm1
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def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
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T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
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bits<1> imm;
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let Inst{4} = 0b1;
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let Inst{3} = imm;
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let Inst{2-0} = 0b000;
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let Unpredictable{4} = 0b1;
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let Unpredictable{2-0} = 0b111;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//
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@ -5441,7 +5441,7 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
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Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
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Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
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Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
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Mnemonic.startswith("aes") || Mnemonic == "hvc" ||
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Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
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Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
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(FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
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// These mnemonics are never predicable
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@ -212,6 +212,10 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
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@ -2119,6 +2123,54 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
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return S;
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}
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static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Pred = fieldFromInstruction(Insn, 28, 4);
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unsigned Rn = fieldFromInstruction(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction(Insn, 0, 4);
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if (Pred == 0xF)
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return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
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return MCDisassembler::Fail;
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return S;
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}
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static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Imm = fieldFromInstruction(Insn, 9, 1);
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const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
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uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
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if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
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(FeatureBits & ARM::HasV8Ops) == 0 )
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return MCDisassembler::Fail;
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// Decoder can be called from DecodeTST, which does not check the full
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// encoding is valid.
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if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
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fieldFromInstruction(Insn, 4,4) != 0)
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return MCDisassembler::Fail;
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if (fieldFromInstruction(Insn, 10,10) != 0 ||
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fieldFromInstruction(Insn, 0,4) != 0)
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S = MCDisassembler::SoftFail;
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Inst.setOpcode(ARM::SETPAN);
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Inst.addOperand(MCOperand::CreateImm(Imm));
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return S;
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}
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static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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@ -172,3 +172,35 @@
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//CHECK-V8: error: instruction requires: armv8.1a
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//CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0]
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//CHECK-V8: ^
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setpan #0
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//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6]
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//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1]
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//CHECK-V8: error: instruction requires: armv8.1a
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//CHECK-V8: setpan #0
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//CHECK-V8: ^
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setpan #1
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//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6]
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//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1]
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//CHECK-V8: error: instruction requires: armv8.1a
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//CHECK-V8: setpan #1
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//CHECK-V8: ^
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setpan
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setpan #-1
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setpan #2
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//CHECK-ERROR: error: too few operands for instruction
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//CHECK-ERROR: setpan
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: setpan #-1
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: setpan #2
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//CHECK-ERROR: ^
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it eq
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setpaneq #0
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//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified
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//CHECK-THUMB-ERROR: setpaneq #0
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//CHECK-THUMB-ERROR: ^
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@ -34,3 +34,19 @@
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# CHECK-V8: [0x42,0x0f,0x92,0xf3]
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# CHECK-V8: warning: invalid instruction encoding
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# CHECK-V8: [0x42,0x0f,0xa1,0xf2]
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# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN
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# uses the encoding for the invalid NV predicate operand. This test checks that
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# the disassembler is correctly disambiguating and decoding these instructions.
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[0x00 0x00 0x10 0xf1]
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# CHECK: setpan #0
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[0x00 0x02 0x10 0xf1]
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# CHECK: setpan #1
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[0x00 0x00 0x10 0xe1]
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# CHECK: tst r0, r0
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[0x00 0x02 0x10 0xe1]
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# CHECK: tst r0, r0, lsl #4
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@ -96,3 +96,15 @@
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# CHECK-V8: warning: invalid instruction encoding
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# CHECK-V8: [0xa2,0xff,0x42,0x0f]
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# CHECK-V8: ^
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[0x10,0xb6]
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# CHECK-V81a: setpan #0
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# CHECK-V8: warning: invalid instruction encoding
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# CHECK-V8: [0x10,0xb6]
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# CHECK-V8: ^
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[0x18,0xb6]
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# CHECK-V81a: setpan #1
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# CHECK-V8: warning: invalid instruction encoding
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# CHECK-V8: [0x18,0xb6]
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# CHECK-V8: ^
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