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Add support for compiling varargs functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6325 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
12745c55e1
commit
5b1b47b824
@ -87,7 +87,8 @@ Xdefine PANIC printf
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%term Call=CallOPCODE
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%term Shl=ShlOPCODE
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%term Shr=ShrOPCODE
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/* 30...46 are unused */
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%term VaArg=VarArgOPCODE
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/* 32...46 are unused */
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/*
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* The foll. values should match the constants in InstrForest.h
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*/
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@ -256,6 +257,7 @@ reg: Call = 61 (20); /* just ignore the operands! */
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reg: Shl(reg,reg) = 62 (20); /* 1 for issue restrictions */
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reg: Shr(reg,reg) = 63 (20); /* 1 for issue restrictions */
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reg: Phi(reg,reg) = 64 (0);
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reg: VaArg(reg) = 65 (40); /* load from stack then incr */
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/*
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* Finally, leaf nodes of expression trees.
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@ -22,6 +22,7 @@
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#include "llvm/Function.h"
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#include "llvm/Constants.h"
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#include "llvm/ConstantHandling.h"
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#include "llvm/Intrinsics.h"
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#include "Support/MathExtras.h"
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#include <math.h>
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@ -1298,6 +1299,46 @@ AllUsesAreBranches(const Instruction* setccI)
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return true;
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}
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// Generate code for any intrinsic that needs a special code sequence
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// instead of a regular call. If not that kind of intrinsic, do nothing.
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// Returns true if code was generated, otherwise false.
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//
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bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr,
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TargetMachine &target,
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std::vector<MachineInstr*>& mvec)
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{
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switch (iid) {
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case LLVMIntrinsic::va_start: {
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// Get the address of the first vararg value on stack and copy it to
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// the argument of va_start(va_list* ap).
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bool ignore;
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Function* func = cast<Function>(callInstr.getParent()->getParent());
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int numFixedArgs = func->getFunctionType()->getNumParams();
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int fpReg = target.getFrameInfo().getIncomingArgBaseRegNum();
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int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
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int firstVarArgOff = numFixedArgs * argSize + target.getFrameInfo().
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getFirstIncomingArgOffset(MachineFunction::get(func), ignore);
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mvec.push_back(BuildMI(V9::ADD, 3).addMReg(fpReg).addSImm(firstVarArgOff).
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addReg(callInstr.getOperand(1)));
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return true;
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}
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case LLVMIntrinsic::va_end:
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return true; // no-op on Sparc
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case LLVMIntrinsic::va_copy:
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// Simple copy of current va_list (arg2) to new va_list (arg1)
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mvec.push_back(BuildMI(V9::OR, 3).
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addMReg(target.getRegInfo().getZeroRegNum()).
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addReg(callInstr.getOperand(2)).
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addReg(callInstr.getOperand(1)));
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return true;
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default:
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return false;
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}
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}
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//******************* Externally Visible Functions *************************/
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//------------------------------------------------------------------------
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@ -2101,96 +2142,112 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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//
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CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
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Value *callee = callInstr->getCalledValue();
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Function* calledFunc = dyn_cast<Function>(callee);
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// Create hidden virtual register for return address with type void*
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TmpInstruction* retAddrReg =
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new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
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MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
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// Generate the machine instruction and its operands.
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// Use CALL for direct function calls; this optimistically assumes
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// the PC-relative address fits in the CALL address field (22 bits).
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// Use JMPL for indirect calls.
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// Check if this is an intrinsic function that needs a special code
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// sequence (e.g., va_start). Indirect calls cannot be special.
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//
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if (isa<Function>(callee)) // direct function call
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M = BuildMI(V9::CALL, 1).addPCDisp(callee);
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else // indirect function call
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M = BuildMI(V9::JMPLCALL, 3).addReg(callee).addSImm((int64_t)0)
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.addRegDef(retAddrReg);
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mvec.push_back(M);
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bool specialIntrinsic = false;
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LLVMIntrinsic::ID iid;
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if (calledFunc && (iid=(LLVMIntrinsic::ID)calledFunc->getIntrinsicID()))
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specialIntrinsic = CodeGenIntrinsic(iid, *callInstr, target, mvec);
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const FunctionType* funcType =
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cast<FunctionType>(cast<PointerType>(callee->getType())
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->getElementType());
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bool isVarArgs = funcType->isVarArg();
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bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
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// Use a descriptor to pass information about call arguments
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// to the register allocator. This descriptor will be "owned"
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// and freed automatically when the MachineCodeForInstruction
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// object for the callInstr goes away.
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CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr,
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retAddrReg, isVarArgs, noPrototype);
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assert(callInstr->getOperand(0) == callee
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&& "This is assumed in the loop below!");
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for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
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// If not, generate the normal call sequence for the function.
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// This can also handle any intrinsics that are just function calls.
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//
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if (! specialIntrinsic)
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{
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Value* argVal = callInstr->getOperand(i);
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Instruction* intArgReg = NULL;
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// Create hidden virtual register for return address with type void*
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TmpInstruction* retAddrReg =
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new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
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MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
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// Generate the machine instruction and its operands.
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// Use CALL for direct function calls; this optimistically assumes
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// the PC-relative address fits in the CALL address field (22 bits).
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// Use JMPL for indirect calls.
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//
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if (calledFunc) // direct function call
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M = BuildMI(V9::CALL, 1).addPCDisp(callee);
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else // indirect function call
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M = BuildMI(V9::JMPLCALL, 3).addReg(callee).addSImm((int64_t)0)
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.addRegDef(retAddrReg);
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mvec.push_back(M);
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const FunctionType* funcType =
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cast<FunctionType>(cast<PointerType>(callee->getType())
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->getElementType());
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bool isVarArgs = funcType->isVarArg();
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bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
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// Use a descriptor to pass information about call arguments
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// to the register allocator. This descriptor will be "owned"
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// and freed automatically when the MachineCodeForInstruction
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// object for the callInstr goes away.
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CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr,
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retAddrReg, isVarArgs,noPrototype);
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// Check for FP arguments to varargs functions.
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// Any such argument in the first $K$ args must be passed in an
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// integer register, where K = #integer argument registers.
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if (isVarArgs && argVal->getType()->isFloatingPoint())
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assert(callInstr->getOperand(0) == callee
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&& "This is assumed in the loop below!");
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for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
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{
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// If it is a function with no prototype, pass value
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// as an FP value as well as a varargs value
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if (noPrototype)
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argDesc->getArgInfo(i-1).setUseFPArgReg();
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// If this arg. is in the first $K$ regs, add a copy
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// float-to-int instruction to pass the value as an integer.
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if (i <= target.getRegInfo().GetNumOfIntArgRegs())
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Value* argVal = callInstr->getOperand(i);
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Instruction* intArgReg = NULL;
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// Check for FP arguments to varargs functions.
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// Any such argument in the first $K$ args must be passed in an
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// integer register, where K = #integer argument registers.
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if (isVarArgs && argVal->getType()->isFloatingPoint())
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{
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MachineCodeForInstruction &destMCFI =
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MachineCodeForInstruction::get(callInstr);
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intArgReg = new TmpInstruction(Type::IntTy, argVal);
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destMCFI.addTemp(intArgReg);
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// If it is a function with no prototype, pass value
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// as an FP value as well as a varargs value
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if (noPrototype)
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argDesc->getArgInfo(i-1).setUseFPArgReg();
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// If this arg. is in the first $K$ regs, add a copy
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// float-to-int instruction to pass the value as an integer.
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if (i <= target.getRegInfo().getNumOfIntArgRegs())
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{
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MachineCodeForInstruction &destMCFI =
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MachineCodeForInstruction::get(callInstr);
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intArgReg = new TmpInstruction(Type::IntTy, argVal);
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destMCFI.addTemp(intArgReg);
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std::vector<MachineInstr*> copyMvec;
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target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
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callInstr->getParent()->getParent(),
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argVal, (TmpInstruction*) intArgReg,
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copyMvec, destMCFI);
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mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end());
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std::vector<MachineInstr*> copyMvec;
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target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
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callInstr->getParent()->getParent(),
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argVal, (TmpInstruction*) intArgReg,
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copyMvec, destMCFI);
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mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end());
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argDesc->getArgInfo(i-1).setUseIntArgReg();
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argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
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argDesc->getArgInfo(i-1).setUseIntArgReg();
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argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
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}
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else
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// Cannot fit in first $K$ regs so pass arg on stack
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argDesc->getArgInfo(i-1).setUseStackSlot();
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}
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else
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// Cannot fit in first $K$ regs so pass the arg on the stack
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argDesc->getArgInfo(i-1).setUseStackSlot();
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if (intArgReg)
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mvec.back()->addImplicitRef(intArgReg);
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mvec.back()->addImplicitRef(argVal);
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}
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if (intArgReg)
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mvec.back()->addImplicitRef(intArgReg);
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mvec.back()->addImplicitRef(argVal);
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// Add the return value as an implicit ref. The call operands
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// were added above.
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if (callInstr->getType() != Type::VoidTy)
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mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
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// For the CALL instruction, the ret. addr. reg. is also implicit
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if (isa<Function>(callee))
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mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
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// delay slot
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mvec.push_back(BuildMI(V9::NOP, 0));
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}
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// Add the return value as an implicit ref. The call operands
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// were added above.
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if (callInstr->getType() != Type::VoidTy)
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mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
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// For the CALL instruction, the ret. addr. reg. is also implicit
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if (isa<Function>(callee))
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mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
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// delay slot
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mvec.push_back(BuildMI(V9::NOP, 0));
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break;
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}
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@ -2225,6 +2282,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 64: // reg: Phi(reg,reg)
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break; // don't forward the value
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case 65: // reg: VaArg(reg)
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{
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// Use value initialized by va_start as pointer to args on the stack.
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// Load argument via current pointer value, then increment pointer.
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int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
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Instruction* vaArgI = subtreeRoot->getInstruction();
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mvec.push_back(BuildMI(V9::LDX, 3).addReg(vaArgI->getOperand(0)).
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addSImm(0).addRegDef(vaArgI));
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mvec.push_back(BuildMI(V9::ADD, 3).addReg(vaArgI->getOperand(0)).
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addSImm(argSize).addRegDef(vaArgI->getOperand(0)));
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break;
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}
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case 71: // reg: VReg
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case 72: // reg: Constant
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break; // don't forward the value
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@ -374,8 +374,8 @@ public:
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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// and float args (usually 32: %f0 - %f31)
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//
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unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
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unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
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unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
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unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
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// The following methods are used to color special live ranges (e.g.
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// function args and return values etc.) with specific hardware registers
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@ -17,6 +17,8 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Intrinsics.h"
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namespace {
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struct InsertPrologEpilogCode : public MachineFunctionPass {
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@ -93,6 +95,34 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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mvec.push_back(M);
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}
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// For varargs function bodies, insert instructions to copy incoming
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// register arguments for the ... list to the stack.
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// The first K=6 arguments are always received via int arg regs
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// (%i0 ... %i5 if K=6) .
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// By copying the varargs arguments to the stack, va_arg() then can
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// simply assume that all vararg arguments are in an array on the stack.
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//
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if (MF.getFunction()->getFunctionType()->isVarArg()) {
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int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
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int numArgRegs = TM.getRegInfo().getNumOfIntArgRegs();
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if (numFixedArgs < numArgRegs) {
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bool ignore;
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int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
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TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::i0);
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int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
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int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
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int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);
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int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
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for (int i=numFixedArgs; i < numArgRegs; ++i) {
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mvec.push_back(BuildMI(V9::STX, 3).addMReg(firstArgReg+i).
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addMReg(fpReg).addSImm(nextArgOffset));
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nextArgOffset += argSize;
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}
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}
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}
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MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end());
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}
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