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The getRegForInlineAsmConstraint function should only accept MVT value types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2013-06-22 18:37:38 +00:00
parent 5729b8ea01
commit 5b3fca50a0
26 changed files with 28 additions and 28 deletions
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2
include/llvm/Target/TargetLowering.h
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@ -2229,7 +2229,7 @@ public:
/// this returns a register number of 0 and a null register class pointer..
virtual std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1992,7 +1992,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint[0] != '{')
return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");

2
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2932,7 +2932,7 @@ AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::pair<unsigned, const TargetRegisterClass*>
AArch64TargetLowering::getRegForInlineAsmConstraint(
const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':

2
lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -245,7 +245,7 @@ public:
SelectionDAG &DAG) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
private:
const InstrItineraryData *Itins;

2
lib/Target/ARM/ARMISelLowering.cpp
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@ -10310,7 +10310,7 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
RCPair
ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
// GCC ARM Constraint Letters
switch (Constraint[0]) {

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -349,7 +349,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is

4
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1590,11 +1590,11 @@ const {
std::pair<unsigned, const TargetRegisterClass*>
HexagonTargetLowering::getRegForInlineAsmConstraint(const
std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r': // R0-R31
switch (VT.getSimpleVT().SimpleTy) {
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i32:

2
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -150,7 +150,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
// Intrinsics
virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op,

2
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -1127,7 +1127,7 @@ MBlazeTargetLowering::getSingleConstraintMatchWeight(
/// to an LLVM register class, return a register of 0 and the register class
/// pointer.
std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':

2
lib/Target/MBlaze/MBlazeISelLowering.h
View File

@ -165,7 +165,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;

2
lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -226,7 +226,7 @@ MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
std::pair<unsigned, const TargetRegisterClass*>
MSP430TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
// GCC Constraint Letters
switch (Constraint[0]) {

2
lib/Target/MSP430/MSP430ISelLowering.h
View File

@ -98,7 +98,7 @@ namespace llvm {
TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
/// isTruncateFree - Return true if it's free to truncate a value of type
/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in

2
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -2885,7 +2885,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
/// to an LLVM register class, return a register of 0 and the register class
/// pointer.
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
{
if (Constraint.size() == 1) {
switch (Constraint[0]) {

2
lib/Target/Mips/MipsISelLowering.h
View File

@ -435,7 +435,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is

2
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -1421,7 +1421,7 @@ NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
std::pair<unsigned, const TargetRegisterClass *>
NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'c':

2
lib/Target/NVPTX/NVPTXISelLowering.h
View File

@ -108,7 +108,7 @@ public:
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
virtual SDValue LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -7514,7 +7514,7 @@ PPCTargetLowering::getSingleConstraintMatchWeight(
std::pair<unsigned, const TargetRegisterClass*>
PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {

2
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -420,7 +420,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area. This is the actual

2
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1906,7 +1906,7 @@ SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
std::pair<unsigned, const TargetRegisterClass*>
SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':

2
lib/Target/Sparc/SparcISelLowering.h
View File

@ -68,7 +68,7 @@ namespace llvm {
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }

2
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -360,7 +360,7 @@ getSingleConstraintMatchWeight(AsmOperandInfo &info,
}
std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
if (Constraint.size() == 1) {
// GCC Constraint Letters
switch (Constraint[0]) {

2
lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -129,7 +129,7 @@ public:
virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
virtual std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const LLVM_OVERRIDE;
MVT VT) const LLVM_OVERRIDE;
virtual TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
virtual TargetLowering::ConstraintWeight

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -18423,7 +18423,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::pair<unsigned, const TargetRegisterClass*>
X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
// First, see if this is a constraint that directly corresponds to an LLVM
// register class.
if (Constraint.size() == 1) {
@ -18490,7 +18490,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
if (!Subtarget->hasSSE1()) break;
switch (VT.getSimpleVT().SimpleTy) {
switch (VT.SimpleTy) {
default: break;
// Scalar SSE types.
case MVT::f32:

2
lib/Target/X86/X86ISelLowering.h
View File

@ -610,7 +610,7 @@ namespace llvm {
/// error, this returns a register number of 0.
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.

2
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1582,7 +1582,7 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
std::pair<unsigned, const TargetRegisterClass*>
XCoreTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;

2
lib/Target/XCore/XCoreISelLowering.h
View File

@ -158,7 +158,7 @@ namespace llvm {
// Inline asm support
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
MVT VT) const;
// Expand specifics
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;