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[mips] Clang generates unaligned offset for MSA instruction st.d
Differential Revision: https://reviews.llvm.org/D19475 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277323 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hrvoje Varga
parent
5bfb1b8c4e
commit
5c02c44a28
@ -108,8 +108,26 @@ bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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@ -78,8 +78,17 @@ private:
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SDValue &Offset) const;
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/// Match addr+simm10 and addr
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virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset);
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virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset);
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@ -1098,7 +1098,13 @@ def addrRegImm :
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def addrDefault :
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ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
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def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
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def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10", [frameindex]>;
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def addrimm10lsl1 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl1",
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[frameindex]>;
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def addrimm10lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl2",
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[frameindex]>;
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def addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3",
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[frameindex]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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@ -2308,9 +2308,12 @@ class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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}
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class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
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class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
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class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
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class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
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class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
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mem_simm10_lsl1, addrimm10lsl1>;
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class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
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mem_simm10_lsl2, addrimm10lsl2>;
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class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
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mem_simm10_lsl3, addrimm10lsl3>;
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class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
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class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
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@ -2641,9 +2644,12 @@ class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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}
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class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
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class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
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class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
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class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
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class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
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mem_simm10_lsl1, addrimm10lsl1>;
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class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
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mem_simm10_lsl2, addrimm10lsl2>;
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class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
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mem_simm10_lsl3, addrimm10lsl3>;
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class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
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MSA128BOpnd>;
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@ -3523,16 +3529,16 @@ class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
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def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
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(COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
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def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
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def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
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def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
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def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
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def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
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def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
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def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
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(ST_H MSA128H:$ws, addrimm10:$addr)>;
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def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
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(ST_W MSA128W:$ws, addrimm10:$addr)>;
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def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
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(ST_D MSA128D:$ws, addrimm10:$addr)>;
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def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
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(ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
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def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
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(ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
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def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
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(ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
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class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
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RegisterOperand ROWS = ROWD,
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@ -293,20 +293,25 @@ bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
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}
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/// Match frameindex+offset and frameindex|offset
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bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
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SDValue &Offset,
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unsigned OffsetBits) const {
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bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
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SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
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unsigned ShiftAmount = 0) const {
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isIntN(OffsetBits, CN->getSExtValue())) {
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if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
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EVT ValTy = Addr.getValueType();
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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else {
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Base = Addr.getOperand(0);
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// If base is a FI, additional offset calculation is done in
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// eliminateFrameIndex, otherwise we need to check the alignment
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if (OffsetToAlignment(CN->getZExtValue(), 1 << ShiftAmount) != 0)
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return false;
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
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ValTy);
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@ -392,17 +397,6 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
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return false;
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}
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bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
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return true;
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return false;
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}
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/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
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bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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@ -478,15 +472,49 @@ bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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return selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrRegImm10(Addr, Base, Offset))
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bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrDefault(Addr, Base, Offset))
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
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return true;
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return false;
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return selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
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return true;
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return selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
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return true;
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return selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
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return true;
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return selectAddrDefault(Addr, Base, Offset);
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}
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// Select constant vector splats.
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@ -44,7 +44,8 @@ private:
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bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
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unsigned OffsetBits) const;
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unsigned OffsetBits,
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unsigned ShiftAmount) const;
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bool selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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@ -58,9 +59,6 @@ private:
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bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectAddrRegImm11(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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@ -82,8 +80,17 @@ private:
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bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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/// \brief Select constant vector splats.
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bool selectVSplat(SDNode *N, APInt &Imm,
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@ -22,6 +22,59 @@ declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
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; CHECK: st.b
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; CHECK: .size llvm_mips_ld_b_test
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;
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define void @llvm_mips_ld_b_unaligned_test() nounwind {
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entry:
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%0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
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%1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 9)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
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ret void
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}
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; CHECK: llvm_mips_ld_b_unaligned_test:
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; CHECK: ld.b [[R1:\$w[0-9]+]], 9(
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; CHECK: st.b
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; CHECK: .size llvm_mips_ld_b_unaligned_test
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;
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define void @llvm_mips_ld_b_valid_range_tests() nounwind {
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entry:
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%0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
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%1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -512)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
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%2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 511)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_ld_b_RES
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ret void
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}
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; CHECK: llvm_mips_ld_b_valid_range_tests:
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; CHECK: ld.b [[R1:\$w[0-9]+]], -512(
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; CHECK: st.b
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; CHECK: ld.b [[R1:\$w[0-9]+]], 511(
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; CHECK: st.b
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; CHECK: .size llvm_mips_ld_b_valid_range_tests
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;
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define void @llvm_mips_ld_b_invalid_range_tests() nounwind {
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entry:
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%0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
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%1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -513)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
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%2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 512)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_ld_b_RES
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ret void
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}
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; CHECK: llvm_mips_ld_b_invalid_range_tests:
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; CHECK: addiu $3, $2, -513
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; CHECK: ld.b [[R1:\$w[0-9]+]], 0(
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; CHECK: st.b
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; CHECK: addiu $2, $2, 512
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; CHECK: ld.b [[R1:\$w[0-9]+]], 0(
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; CHECK: st.b
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; CHECK: .size llvm_mips_ld_b_invalid_range_tests
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;
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@llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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@ -40,6 +93,60 @@ declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
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; CHECK: st.h
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; CHECK: .size llvm_mips_ld_h_test
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;
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define void @llvm_mips_ld_h_unaligned_test() nounwind {
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entry:
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%0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
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%1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 9)
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store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
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ret void
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}
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; CHECK: llvm_mips_ld_h_unaligned_test:
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; CHECK: addiu $2, $2, 9
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; CHECK: ld.h [[R1:\$w[0-9]+]], 0($2)
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; CHECK: st.h
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; CHECK: .size llvm_mips_ld_h_unaligned_test
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;
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define void @llvm_mips_ld_h_valid_range_tests() nounwind {
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entry:
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%0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
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%1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 -1024)
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store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
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%2 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 1022)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_ld_h_RES
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ret void
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}
|
||||
|
||||
; CHECK: llvm_mips_ld_h_valid_range_tests:
|
||||
; CHECK: ld.h [[R1:\$w[0-9]+]], -1024(
|
||||
; CHECK: st.h
|
||||
; CHECK: ld.h [[R1:\$w[0-9]+]], 1022(
|
||||
; CHECK: st.h
|
||||
; CHECK: .size llvm_mips_ld_h_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_h_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
|
||||
%1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 -1026)
|
||||
store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
|
||||
%2 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 1024)
|
||||
store <8 x i16> %2, <8 x i16>* @llvm_mips_ld_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_h_invalid_range_tests:
|
||||
; CHECK: addiu $3, $2, -1026
|
||||
; CHECK: ld.h [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.h
|
||||
; CHECK: addiu $2, $2, 1024
|
||||
; CHECK: ld.h [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.h
|
||||
; CHECK: .size llvm_mips_ld_h_invalid_range_tests
|
||||
;
|
||||
|
||||
@llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
@ -61,6 +168,59 @@ declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
|
||||
@llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_ld_w_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
|
||||
%1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 9)
|
||||
store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_w_unaligned_test:
|
||||
; CHECK: addiu $2, $2, 9
|
||||
; CHECK: ld.w [[R1:\$w[0-9]+]], 0($2)
|
||||
; CHECK: st.w
|
||||
; CHECK: .size llvm_mips_ld_w_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_w_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
|
||||
%1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 -2048)
|
||||
store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
|
||||
%2 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 2044)
|
||||
store <4 x i32> %2, <4 x i32>* @llvm_mips_ld_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_w_valid_range_tests:
|
||||
; CHECK: ld.w [[R1:\$w[0-9]+]], -2048(
|
||||
; CHECK: st.w
|
||||
; CHECK: ld.w [[R1:\$w[0-9]+]], 2044(
|
||||
; CHECK: st.w
|
||||
; CHECK: .size llvm_mips_ld_w_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_w_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
|
||||
%1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 -2052)
|
||||
store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
|
||||
%2 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 2048)
|
||||
store <4 x i32> %2, <4 x i32>* @llvm_mips_ld_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_w_invalid_range_tests:
|
||||
; CHECK: addiu $3, $2, -2052
|
||||
; CHECK: ld.w [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.w
|
||||
; CHECK: addiu $2, $2, 2048
|
||||
; CHECK: ld.w [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.w
|
||||
; CHECK: .size llvm_mips_ld_w_invalid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_d_test() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
|
||||
@ -76,6 +236,62 @@ declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
|
||||
; CHECK: st.d
|
||||
; CHECK: .size llvm_mips_ld_d_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_d_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
|
||||
%1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 9)
|
||||
store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_d_unaligned_test:
|
||||
; CHECK: addiu $2, $2, 9
|
||||
; CHECK: ld.d [[R1:\$w[0-9]+]], 0($2)
|
||||
; CHECK: st.d
|
||||
; CHECK: .size llvm_mips_ld_d_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_d_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
|
||||
%1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 -4096)
|
||||
store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
|
||||
%2 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 4088)
|
||||
store <2 x i64> %2, <2 x i64>* @llvm_mips_ld_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_d_valid_range_tests:
|
||||
; CHECK: ld.d [[R1:\$w[0-9]+]], -4096(
|
||||
; CHECK: st.d
|
||||
; CHECK: ld.d [[R1:\$w[0-9]+]], 4088(
|
||||
; CHECK: st.d
|
||||
; CHECK: .size llvm_mips_ld_d_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_ld_d_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
|
||||
%1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 -4104)
|
||||
store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
|
||||
%2 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 4096)
|
||||
store <2 x i64> %2, <2 x i64>* @llvm_mips_ld_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_ld_d_invalid_range_tests:
|
||||
; CHECK: addiu $3, $2, -4104
|
||||
; CHECK: ld.d [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.d
|
||||
; CHECK: addiu $2, $2, 4096
|
||||
; CHECK: ld.d [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: st.d
|
||||
; CHECK: .size llvm_mips_ld_d_invalid_range_tests
|
||||
;
|
||||
|
||||
|
||||
|
||||
@llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
@ -94,6 +310,55 @@ declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], 16(
|
||||
; CHECK: .size llvm_mips_st_b_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_b_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG
|
||||
%1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
|
||||
tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 9)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_b_unaligned_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], 9(
|
||||
; CHECK: .size llvm_mips_st_b_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_b_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG
|
||||
%1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
|
||||
tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 -512)
|
||||
tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 511)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_b_valid_range_tests:
|
||||
; CHECK: ld.b
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], -512(
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], 511(
|
||||
; CHECK: .size llvm_mips_st_b_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_b_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG
|
||||
%1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
|
||||
tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 -513)
|
||||
tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 512)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_b_invalid_range_tests:
|
||||
; CHECK: addiu $2, $1, -513
|
||||
; CHECK: ld.b
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: addiu $1, $1, 512
|
||||
; CHECK: st.b [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: .size llvm_mips_st_b_invalid_range_tests
|
||||
;
|
||||
|
||||
@llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
@ -112,6 +377,56 @@ declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], 16(
|
||||
; CHECK: .size llvm_mips_st_h_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_h_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG
|
||||
%1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
|
||||
tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 9)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_h_unaligned_test:
|
||||
; CHECK: addiu $1, $1, 9
|
||||
; CHECK: ld.h
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], 0($1)
|
||||
; CHECK: .size llvm_mips_st_h_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_h_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG
|
||||
%1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
|
||||
tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 -1024)
|
||||
tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 1022)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_h_valid_range_tests:
|
||||
; CHECK: ld.h
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], -1024(
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], 1022(
|
||||
; CHECK: .size llvm_mips_st_h_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_h_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG
|
||||
%1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
|
||||
tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 -1026)
|
||||
tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 1024)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_h_invalid_range_tests:
|
||||
; CHECK: addiu $2, $1, -1026
|
||||
; CHECK: ld.h
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: addiu $1, $1, 1024
|
||||
; CHECK: st.h [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: .size llvm_mips_st_h_invalid_range_tests
|
||||
;
|
||||
|
||||
@llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
@ -130,6 +445,56 @@ declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], 16(
|
||||
; CHECK: .size llvm_mips_st_w_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_w_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG
|
||||
%1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
|
||||
tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 9)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_w_unaligned_test:
|
||||
; CHECK: addiu $1, $1, 9
|
||||
; CHECK: ld.w
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], 0($1)
|
||||
; CHECK: .size llvm_mips_st_w_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_w_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG
|
||||
%1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
|
||||
tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 -2048)
|
||||
tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 2044)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_w_valid_range_tests:
|
||||
; CHECK: ld.w
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], -2048(
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], 2044(
|
||||
; CHECK: .size llvm_mips_st_w_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_w_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG
|
||||
%1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
|
||||
tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 -2052)
|
||||
tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 2048)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_w_invalid_range_tests:
|
||||
; CHECK: addiu $2, $1, -2052
|
||||
; CHECK: ld.w
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: addiu $1, $1, 2048
|
||||
; CHECK: st.w [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: .size llvm_mips_st_w_invalid_range_tests
|
||||
;
|
||||
|
||||
@llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
@ -148,3 +513,52 @@ declare void @llvm.mips.st.d(<2 x i64>, i8*, i32) nounwind
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], 16(
|
||||
; CHECK: .size llvm_mips_st_d_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_d_unaligned_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG
|
||||
%1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
|
||||
tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 9)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_d_unaligned_test:
|
||||
; CHECK: addiu $1, $1, 9
|
||||
; CHECK: ld.d
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], 0($1)
|
||||
; CHECK: .size llvm_mips_st_d_unaligned_test
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_d_valid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG
|
||||
%1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
|
||||
tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 -4096)
|
||||
tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 4088)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_d_valid_range_tests:
|
||||
; CHECK: ld.d
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], -4096(
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], 4088(
|
||||
; CHECK: .size llvm_mips_st_d_valid_range_tests
|
||||
;
|
||||
|
||||
define void @llvm_mips_st_d_invalid_range_tests() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG
|
||||
%1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
|
||||
tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 -4104)
|
||||
tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 4096)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_st_d_invalid_range_tests:
|
||||
; CHECK: addiu $2, $1, -4104
|
||||
; CHECK: ld.d
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: addiu $1, $1, 4096
|
||||
; CHECK: st.d [[R1:\$w[0-9]+]], 0(
|
||||
; CHECK: .size llvm_mips_st_d_invalid_range_tests
|
||||
;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user