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ARMAsmParser: Take MCInst param by const-ref

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(Broken out from http://reviews.llvm.org/D11167)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242160 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hans Wennborg 2015-07-14 16:39:01 +00:00
parent 0ea5f00226
commit 5c63c6a361
1 changed files with 9 additions and 8 deletions
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17
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -189,9 +189,9 @@ class ARMAsmParser : public MCTargetAsmParser {
return getParser().Error(L, Msg, Ranges); return getParser().Error(L, Msg, Ranges);
} }
bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands, bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
unsigned ListNo, bool IsARPop = false); unsigned ListNo, bool IsARPop = false);
bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands, bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
unsigned ListNo); unsigned ListNo);
int tryParseRegister(); int tryParseRegister();
@ -6033,8 +6033,9 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
// return 'true' if register list contains non-low GPR registers, // return 'true' if register list contains non-low GPR registers,
// 'false' otherwise. If Reg is in the register list or is HiReg, set // 'false' otherwise. If Reg is in the register list or is HiReg, set
// 'containsReg' to true. // 'containsReg' to true.
static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
unsigned HiReg, bool &containsReg) { unsigned Reg, unsigned HiReg,
bool &containsReg) {
containsReg = false; containsReg = false;
for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
unsigned OpReg = Inst.getOperand(i).getReg(); unsigned OpReg = Inst.getOperand(i).getReg();
@ -6049,8 +6050,8 @@ static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
// Check if the specified regisgter is in the register list of the inst, // Check if the specified regisgter is in the register list of the inst,
// starting at the indicated operand number. // starting at the indicated operand number.
static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
unsigned OpReg = Inst.getOperand(i).getReg(); unsigned OpReg = Inst.getOperand(i).getReg();
if (OpReg == Reg) if (OpReg == Reg)
return true; return true;
@ -6068,7 +6069,7 @@ static bool instIsBreakpoint(const MCInst &Inst) {
} }
bool ARMAsmParser::validatetLDMRegList(MCInst Inst, bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
const OperandVector &Operands, const OperandVector &Operands,
unsigned ListNo, bool IsARPop) { unsigned ListNo, bool IsARPop) {
const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
@ -6091,7 +6092,7 @@ bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
return false; return false;
} }
bool ARMAsmParser::validatetSTMRegList(MCInst Inst, bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
const OperandVector &Operands, const OperandVector &Operands,
unsigned ListNo) { unsigned ListNo) {
const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);