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PowerPC inline asm was emitting two output operands

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for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible.  7144566.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2009-08-18 00:18:39 +00:00
parent 4b49cd298a
commit 5cfd4ddece
3 changed files with 34 additions and 26 deletions
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10
lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
View File

@ -507,15 +507,17 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
return false;
}
// At the moment, all inline asm memory operands are a single register.
// In any case, the output of this routine should always be just one
// assembler operand.
bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant,
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
if (MI->getOperand(OpNo).isReg())
printMemRegReg(MI, OpNo);
else
printMemRegImm(MI, OpNo);
assert (MI->getOperand(OpNo).isReg());
printOperand(MI, OpNo);
return false;
}

28
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -143,30 +143,14 @@ namespace {
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
/// inline asm expressions. It is always correct to compute the value into
/// a register. The case of adding a (possibly relocatable) constant to a
/// register can be improved, but it is wrong to substitute Reg+Reg for
/// Reg in an asm, because the load or store opcode would have to change.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
if (!SelectAddrIdx(Op, Op, Op0, Op1))
SelectAddrImm(Op, Op, Op0, Op1);
break;
case 'o': // offsetable
if (!SelectAddrImm(Op, Op, Op0, Op1)) {
Op0 = Op;
Op1 = getSmallIPtrImm(0);
}
break;
case 'v': // not offsetable
SelectAddrIdxOnly(Op, Op, Op0, Op1);
break;
}
OutOps.push_back(Op0);
OutOps.push_back(Op1);
OutOps.push_back(Op);
return false;
}

22
test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llvm-as < %s | llc -march=ppc32 | grep add
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin10.0"
; It is wrong on powerpc to substitute reg+reg for $0; the stw opcode
; would have to change.
@x = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
define void @foo(i32 %y) nounwind ssp {
entry:
%y_addr = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %y, i32* %y_addr
%0 = load i32* %y_addr, align 4 ; <i32> [#uses=1]
%1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1]
call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind
br label %return
return: ; preds = %entry
ret void
}