From 5d24d88bc7fd65bdc45c805c674a33325aaa00c6 Mon Sep 17 00:00:00 2001
From: Tom Stellard <tstellar@redhat.com>
Date: Tue, 6 Jun 2017 14:16:50 +0000
Subject: [PATCH] AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304797 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |  3 +++
 .../AMDGPU/GlobalISel/legalize-icmp.mir       | 24 +++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index fa259602d48..4fdc270201e 100644
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -47,6 +47,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
   setAction({G_GEP, P2}, Legal);
   setAction({G_GEP, 1, S64}, Legal);
 
+  setAction({G_ICMP, S1}, Legal);
+  setAction({G_ICMP, 1, S32}, Legal);
+
   setAction({G_LOAD, P1}, Legal);
   setAction({G_LOAD, P2}, Legal);
   setAction({G_LOAD, S32}, Legal);
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
new file mode 100644
index 00000000000..ebd473d769b
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_icmp() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_icmp
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %vgpr0
+    %0(s32) = G_CONSTANT i32 0
+    %1(s32) = COPY %vgpr0
+
+    ; CHECK: %2(s1) = G_ICMP intpred(ne), %0(s32), %1
+    %2(s1) = G_ICMP intpred(ne), %0, %1
+...