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[AVX512] Enabling bit logic lowering
Added lowering tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224132 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
fe6c7ee0f0
commit
5dc8ac87f1
@ -1570,6 +1570,13 @@ void X86TargetLowering::resetOperationActions() {
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setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
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setOperationAction(ISD::AND, MVT::v8i32, Legal);
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setOperationAction(ISD::OR, MVT::v8i32, Legal);
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setOperationAction(ISD::XOR, MVT::v8i32, Legal);
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setOperationAction(ISD::AND, MVT::v4i32, Legal);
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setOperationAction(ISD::OR, MVT::v4i32, Legal);
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setOperationAction(ISD::XOR, MVT::v4i32, Legal);
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}
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// SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
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@ -2922,6 +2922,7 @@ let isCodeGenOnly = 1 in {
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///
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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let Predicates = [HasAVX, NoVLX] in {
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defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f256mem,
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
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@ -2952,6 +2953,7 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(loadv2i64 addr:$src2)))], 0>,
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PD, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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101
test/CodeGen/X86/avx512-logic.ll
Normal file
101
test/CodeGen/X86/avx512-logic.ll
Normal file
@ -0,0 +1,101 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: vpandd
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; CHECK: vpandd %zmm
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; CHECK: ret
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define <16 x i32> @vpandd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = and <16 x i32> %a2, %b
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpord
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; CHECK: vpord %zmm
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; CHECK: ret
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define <16 x i32> @vpord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = or <16 x i32> %a2, %b
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpxord
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; CHECK: vpxord %zmm
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; CHECK: ret
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define <16 x i32> @vpxord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = xor <16 x i32> %a2, %b
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpandq
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; CHECK: vpandq %zmm
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; CHECK: ret
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define <8 x i64> @vpandq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%x = and <8 x i64> %a2, %b
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vporq
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; CHECK: vporq %zmm
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; CHECK: ret
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define <8 x i64> @vporq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%x = or <8 x i64> %a2, %b
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vpxorq
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; CHECK: vpxorq %zmm
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; CHECK: ret
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define <8 x i64> @vpxorq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%x = xor <8 x i64> %a2, %b
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ret <8 x i64> %x
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}
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; CHECK-LABEL: orq_broadcast
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; CHECK: vporq LCP{{.*}}(%rip){1to8}, %zmm0, %zmm0
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; CHECK: ret
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define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
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%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: andd512fold
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; CHECK: vpandd (%
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; CHECK: ret
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define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
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entry:
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%a = load <16 x i32>* %x, align 4
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%b = and <16 x i32> %y, %a
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ret <16 x i32> %b
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}
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; CHECK-LABEL: andqbrst
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; CHECK: vpandq (%rdi){1to8}, %zmm
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; CHECK: ret
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define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
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entry:
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%a = load i64* %ap, align 8
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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%d = and <8 x i64> %p1, %c
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ret <8 x i64>%d
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}
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137
test/CodeGen/X86/avx512vl-logic.ll
Normal file
137
test/CodeGen/X86/avx512vl-logic.ll
Normal file
@ -0,0 +1,137 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl | FileCheck %s
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; 256-bit
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; CHECK-LABEL: vpandd256
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; CHECK: vpandd %ymm
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; CHECK: ret
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define <8 x i32> @vpandd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = and <8 x i32> %a2, %b
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ret <8 x i32> %x
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}
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; CHECK-LABEL: vpord256
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; CHECK: vpord %ymm
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; CHECK: ret
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define <8 x i32> @vpord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = or <8 x i32> %a2, %b
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ret <8 x i32> %x
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}
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; CHECK-LABEL: vpxord256
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; CHECK: vpxord %ymm
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; CHECK: ret
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define <8 x i32> @vpxord256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%x = xor <8 x i32> %a2, %b
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ret <8 x i32> %x
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}
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; CHECK-LABEL: vpandq256
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; CHECK: vpandq %ymm
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; CHECK: ret
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define <4 x i64> @vpandq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = and <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK-LABEL: vporq256
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; CHECK: vporq %ymm
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; CHECK: ret
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define <4 x i64> @vporq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = or <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK-LABEL: vpxorq256
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; CHECK: vpxorq %ymm
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; CHECK: ret
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define <4 x i64> @vpxorq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = xor <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; 128-bit
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; CHECK-LABEL: vpandd128
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; CHECK: vpandd %xmm
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; CHECK: ret
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define <4 x i32> @vpandd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
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%x = and <4 x i32> %a2, %b
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ret <4 x i32> %x
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}
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; CHECK-LABEL: vpord128
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; CHECK: vpord %xmm
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; CHECK: ret
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define <4 x i32> @vpord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
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%x = or <4 x i32> %a2, %b
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ret <4 x i32> %x
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}
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; CHECK-LABEL: vpxord128
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; CHECK: vpxord %xmm
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; CHECK: ret
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define <4 x i32> @vpxord128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
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%x = xor <4 x i32> %a2, %b
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ret <4 x i32> %x
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}
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; CHECK-LABEL: vpandq128
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; CHECK: vpandq %xmm
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; CHECK: ret
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define <2 x i64> @vpandq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = and <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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; CHECK-LABEL: vporq128
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; CHECK: vporq %xmm
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; CHECK: ret
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define <2 x i64> @vporq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = or <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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; CHECK-LABEL: vpxorq128
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; CHECK: vpxorq %xmm
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; CHECK: ret
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define <2 x i64> @vpxorq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = xor <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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