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Add a PrintRegUnit helper similar to PrintReg.
Reg-units are named after their root registers, and most units have a single root, so they simply print as 'AL', 'XMM0', etc. The rare dual root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ... The printing piggybacks on the existing register name tables, so no extra const data space is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157754 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -850,6 +850,29 @@ static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
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return OS;
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}
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/// PrintRegUnit - Helper class for printing register units on a raw_ostream.
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///
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/// Register units are named after their root registers:
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///
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/// AL - Single root.
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/// FP0~ST7 - Dual roots.
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///
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/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
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///
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class PrintRegUnit {
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const TargetRegisterInfo *TRI;
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unsigned Unit;
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public:
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PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
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: TRI(tri), Unit(unit) {}
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void print(raw_ostream&) const;
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};
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static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
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PR.print(OS);
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return OS;
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}
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} // End llvm namespace
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#endif
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@ -46,6 +46,27 @@ void PrintReg::print(raw_ostream &OS) const {
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}
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}
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void PrintRegUnit::print(raw_ostream &OS) const {
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// Generic printout when TRI is missing.
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if (!TRI) {
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OS << "Unit~" << Unit;
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return;
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}
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// Check for invalid register units.
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if (Unit >= TRI->getNumRegUnits()) {
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OS << "BadUnit~" << Unit;
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return;
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}
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// Normal units have at least one root.
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MCRegUnitRootIterator Roots(Unit, TRI);
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assert(Roots.isValid() && "Unit has no roots.");
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OS << TRI->getName(*Roots);
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for (++Roots; Roots.isValid(); ++Roots)
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OS << '~' << TRI->getName(*Roots);
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}
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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