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[Hexagon] Adding asrh instruction, removing unused multiclasses.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-11-24 18:04:42 +00:00
parent c1c7be0928
commit 5de3458c18
3 changed files with 17 additions and 40 deletions
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9
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -714,7 +714,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
return isInt<8>(MI->getOperand(2).getImm());
case Hexagon::A2_aslh:
case Hexagon::ASRH:
case Hexagon::A2_asrh:
case Hexagon::A2_sxtb:
case Hexagon::A2_sxth:
case Hexagon::A2_zxtb:
@ -1307,6 +1307,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A4_paslhfnew:
case Hexagon::A4_paslht:
case Hexagon::A4_paslhtnew:
case Hexagon::A4_pasrhf:
case Hexagon::A4_pasrhfnew:
case Hexagon::A4_pasrht:
case Hexagon::A4_pasrhtnew:
case Hexagon::A2_porf:
case Hexagon::A2_porfnew:
case Hexagon::A2_port:
@ -1340,9 +1344,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::COMBINE_rr_cPt:
case Hexagon::COMBINE_rr_cNotPt:
return true;
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps();
}
}

38
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -266,6 +266,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
}
defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
@ -602,46 +603,11 @@ def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
s8ExtPred:$src2,
s8ImmPred:$src3)))]>;
// ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
let isPredicatedNew = isPredNew in
def NAME : ALU32Inst<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2)">,
Requires<[HasV4T]>;
}
multiclass ALU32_2op_Pred2<string mnemonic, bit PredNot> {
let isPredicatedFalse = PredNot in {
defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
}
}
multiclass ALU32_2op_base2<string mnemonic> {
let BaseOpcode = mnemonic in {
let isPredicable = 1, neverHasSideEffects = 1 in
def NAME : ALU32Inst<(outs IntRegs:$dst),
(ins IntRegs:$src1),
"$dst = "#mnemonic#"($src1)">;
let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
neverHasSideEffects = 1 in {
defm Pt_V4 : ALU32_2op_Pred2<mnemonic, 0>;
defm NotPt_V4 : ALU32_2op_Pred2<mnemonic, 1>;
}
}
}
defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
(A2_aslh IntRegs:$src1)>;
def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
(ASRH IntRegs:$src1)>;
(A2_asrh IntRegs:$src1)>;
def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
(A2_sxtb IntRegs:$src1)>;

10
test/MC/Hexagon/inst_asrh.ll Normal file
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@ -0,0 +1,10 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
define i32 @foo (i32 %a)
{
%1 = ashr i32 %a, 16
ret i32 %1
}
; CHECK: 0000 00402070 00c09f52