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If sp offset will be materialized in a register. Clear the offset field of str / ldr.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34010 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-02-07 21:19:58 +00:00
parent 8fdbe560a0
commit 5ebd10e5ac
1 changed files with 10 additions and 8 deletions
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18
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -762,16 +762,18 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
return;
}
bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
if (AddrMode == ARMII::AddrModeTs) {
// Thumb tLDRspi, tSTRspi. These will change to instructions that use
// a different base register.
NumBits = 5;
Mask = (1 << NumBits) - 1;
}
// If this is a thumb spill / restore, we will be using a constpool load to
// materialize the offset.
bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
if (AddrMode == ARMII::AddrModeTs && !isThumSpillRestore) {
if (AddrMode == ARMII::AddrModeTs) {
// Thumb tLDRspi, tSTRspi. These will change to instructions that use
// a different base register.
NumBits = 5;
Mask = (1 << NumBits) - 1;
}
if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
ImmOp.ChangeToImmediate(0);
else {
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
ImmedOffset = ImmedOffset & Mask;
if (isSub)