mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-13 14:46:53 +00:00
assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina
parent
c30088f961
commit
5ef2ec9929
@ -225,14 +225,6 @@ namespace {
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}
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}
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void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (short)MI->getOperand(OpNo).getImmedValue();
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}
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void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
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}
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void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
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@ -245,17 +237,11 @@ namespace {
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if(val>=8192) val=val-16384; // if negative, flip sign
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O << val;
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}
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void printS21ImmOperand(const MachineInstr *MI, unsigned OpNo,
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void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (int)MI->getOperand(OpNo).getImmedValue(); // FIXME (21, not 32!)
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}
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void printS32ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (int)MI->getOperand(OpNo).getImmedValue();
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}
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void printU32ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (unsigned int)MI->getOperand(OpNo).getImmedValue();
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int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
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if(val>=2097152) val=val-4194304; // if negative, flip sign
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O << val;
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}
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void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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@ -639,28 +639,36 @@ unsigned ISel::SelectExpr(SDOperand N) {
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else // false:
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BuildMI(BB, IA64::CMPNE, 2, Result)
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.addReg(IA64::r0).addReg(IA64::r0);
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return Result;
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return Result; // early exit
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}
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case MVT::i64: Opc = IA64::MOVLI32; break;
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case MVT::i64: break;
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}
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int64_t immediate = cast<ConstantSDNode>(N)->getValue();
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if(immediate>>32) { // if our immediate really is big:
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int highPart = immediate>>32;
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int lowPart = immediate&0xFFFFFFFF;
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unsigned dummy = MakeReg(MVT::i64);
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unsigned dummy2 = MakeReg(MVT::i64);
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unsigned dummy3 = MakeReg(MVT::i64);
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BuildMI(BB, IA64::MOVLI32, 1, dummy).addImm(highPart);
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BuildMI(BB, IA64::SHLI, 2, dummy2).addReg(dummy).addImm(32);
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BuildMI(BB, IA64::MOVLI32, 1, dummy3).addImm(lowPart);
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BuildMI(BB, IA64::ADD, 2, Result).addReg(dummy2).addReg(dummy3);
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} else {
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BuildMI(BB, IA64::MOVLI32, 1, Result).addImm(immediate);
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if(immediate==0) { // if the constant is just zero,
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BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r0); // just copy r0
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return Result; // early exit
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}
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return Result;
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if (immediate <= 8191 && immediate >= -8192) {
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// if this constants fits in 14 bits, we use a mov the assembler will
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// turn into: "adds rDest=imm,r0" (and _not_ "andl"...)
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BuildMI(BB, IA64::MOVSIMM14, 1, Result).addSImm(immediate);
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return Result; // early exit
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}
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if (immediate <= 2097151 && immediate >= -2097152) {
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// if this constants fits in 22 bits, we use a mov the assembler will
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// turn into: "addl rDest=imm,r0"
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BuildMI(BB, IA64::MOVSIMM22, 1, Result).addSImm(immediate);
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return Result; // early exit
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}
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/* otherwise, our immediate is big, so we use movl */
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uint64_t Imm = immediate;
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BuildMI(BB, IA64::MOVLIMM64, 1, Result).addU64Imm(Imm);
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return Result;
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}
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case ISD::UNDEF: {
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@ -706,7 +714,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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// first load zero:
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BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
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// ...then conditionally (PR:Tmp1) add 1:
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BuildMI(BB, IA64::CADDIMM22, 3, Result).addReg(dummy)
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BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
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.addImm(1).addReg(Tmp1);
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return Result; // XXX early exit!
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}
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@ -823,15 +831,16 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
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return Result; // early exit
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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if(DestType != MVT::f64) { // integer addition:
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switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
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case 1: // adding a constant that's 14 bits
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BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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return Result; // early exit
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} // fallthrough and emit a reg+reg ADD:
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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} else { // this is a floating point addition
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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@ -868,7 +877,6 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
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BuildMI(BB, IA64::FMS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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return Result; // early exit
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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if(DestType != MVT::f64) { // integer subtraction:
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switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
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@ -876,8 +884,10 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
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BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
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return Result; // early exit
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} // fallthrough and emit a reg+reg SUB:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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} else { // this is a floating point subtraction
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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@ -1311,9 +1321,20 @@ pC = pA OR pB
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case ISD::SETCC: {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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if(ConstantSDNode *CSDN =
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dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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// if we are comparing against a constant zero
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if(CSDN->getValue()==0)
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Tmp2 = IA64::r0; // then we can just compare against r0
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else
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Tmp2 = SelectExpr(N.getOperand(1));
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} else // not comparing against a constant
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Tmp2 = SelectExpr(N.getOperand(1));
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switch (SetCC->getCondition()) {
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default: assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ:
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@ -1351,6 +1372,20 @@ pC = pA OR pB
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else { // if not integer, should be FP. FIXME: what about bools? ;)
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assert(SetCC->getOperand(0).getValueType() != MVT::f32 &&
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"error: SETCC should have had incoming f32 promoted to f64!\n");
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if(ConstantFPSDNode *CFPSDN =
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dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
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// if we are comparing against a constant +0.0 or +1.0
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if(CFPSDN->isExactlyValue(+0.0))
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Tmp2 = IA64::F0; // then we can just compare against f0
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else if(CFPSDN->isExactlyValue(+1.0))
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Tmp2 = IA64::F1; // or f1
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else
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Tmp2 = SelectExpr(N.getOperand(1));
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} else // not comparing against a constant
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Tmp2 = SelectExpr(N.getOperand(1));
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switch (SetCC->getCondition()) {
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default: assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ:
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@ -1836,7 +1871,7 @@ void ISel::Select(SDOperand N) {
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unsigned dummy3 = MakeReg(MVT::i64);
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unsigned dummy4 = MakeReg(MVT::i64);
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BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
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BuildMI(BB, IA64::CADDIMM22, 3, dummy4)
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BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
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.addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
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BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4);
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}
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@ -1858,7 +1893,7 @@ void ISel::Select(SDOperand N) {
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unsigned dummy3 = MakeReg(MVT::i64);
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unsigned dummy4 = MakeReg(MVT::i64);
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BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
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BuildMI(BB, IA64::CADDIMM22, 3, dummy4)
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BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
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.addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
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BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4);
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}
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@ -22,15 +22,8 @@ def s8imm : Operand<i8> {
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def s14imm : Operand<i16> {
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let PrintMethod = "printS14ImmOperand";
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}
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32> {
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let PrintMethod = "printS21ImmOperand";
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}
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def u32imm : Operand<i32> {
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let PrintMethod = "printU32ImmOperand";
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}
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def s32imm : Operand<i32> {
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let PrintMethod = "printS32ImmOperand";
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def s22imm : Operand<i32> {
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let PrintMethod = "printS22ImmOperand";
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}
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def u64imm : Operand<i64> {
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let PrintMethod = "printU64ImmOperand";
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@ -92,13 +85,11 @@ let isTwoAddress = 1 in {
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"($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
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}
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def MOVI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
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def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
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"mov $dst = $imm;;">;
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def MOVLI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
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"movl $dst = $imm;;">;
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def MOVLSI32 : AForm<0x03, 0x0b, (ops GR:$dst, s32imm:$imm),
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"movl $dst = $imm;;">;
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def MOVLI64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
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def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
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"mov $dst = $imm;;">;
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def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
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"movl $dst = $imm;;">;
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def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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@ -109,15 +100,15 @@ def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"xor $dst = $src1, $src2;;">;
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def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shl $dst = $src1, $src2;;">;
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def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
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def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shl $dst = $src1, $imm;;">;
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def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr.u $dst = $src1, $src2;;">;
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def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shr.u $dst = $src1, $imm;;">;
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def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr $dst = $src1, $src2;;">;
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def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shr $dst = $src1, $imm;;">;
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def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
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@ -193,17 +184,17 @@ def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
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"adds $dst = $imm, $src1;;">;
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def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
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"add $dst = $imm, $src1;;">;
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def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
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def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
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"($qp) add $dst = $imm, $src1;;">;
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let isTwoAddress = 1 in {
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def TPCADDIMM22 : AForm<0x03, 0x0b,
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(ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
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(ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
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"($qp) add $dst = $imm, $dst;;">;
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def TPCMPIMM8NE : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src1, s21imm:$imm, GR:$src2, PR:$qp),
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(ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
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"($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
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}
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@ -189,7 +189,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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//fix up the old:
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MI.SetMachineOperandReg(i, IA64::r22);
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MachineInstr* nMI;
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nMI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(Offset);
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nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
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MBB.insert(II, nMI);
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nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
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.addReg(IA64::r22);
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@ -280,7 +280,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
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MBB.insert(MBBI, MI);
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} else { // we use r22 as a scratch register here
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MI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(-NumBytes);
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MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
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// FIXME: MOVLSI32 expects a _u_32imm
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MBB.insert(MBBI, MI); // first load the decrement into r22
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MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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@ -328,7 +328,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
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MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
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MBB.insert(MBBI, MI);
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} else {
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MI=BuildMI(IA64::MOVLI32, 1, IA64::r22).addImm(NumBytes);
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MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
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MBB.insert(MBBI, MI);
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MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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MBB.insert(MBBI, MI);
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