mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-11 21:57:55 +00:00
Modeling the carry bit in the MSR register of the MicroBlaze.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wesley Peck
parent
025c4587d7
commit
5f996d1025
@ -115,14 +115,6 @@ def EGET : FSLGet<0x1B, 0x01, "eget ", int_mblaze_fsl_eget>;
|
||||
def EAGET : FSLGet<0x1B, 0x03, "eaget ", int_mblaze_fsl_eaget>;
|
||||
def ECGET : FSLGet<0x1B, 0x09, "ecget ", int_mblaze_fsl_ecget>;
|
||||
def ECAGET : FSLGet<0x1B, 0x0B, "ecaget ", int_mblaze_fsl_ecaget>;
|
||||
def NGET : FSLGet<0x1B, 0x10, "nget ", int_mblaze_fsl_nget>;
|
||||
def NAGET : FSLGet<0x1B, 0x12, "naget ", int_mblaze_fsl_naget>;
|
||||
def NCGET : FSLGet<0x1B, 0x18, "ncget ", int_mblaze_fsl_ncget>;
|
||||
def NCAGET : FSLGet<0x1B, 0x1A, "ncaget ", int_mblaze_fsl_ncaget>;
|
||||
def NEGET : FSLGet<0x1B, 0x11, "neget ", int_mblaze_fsl_neget>;
|
||||
def NEAGET : FSLGet<0x1B, 0x13, "neaget ", int_mblaze_fsl_neaget>;
|
||||
def NECGET : FSLGet<0x1B, 0x19, "necget ", int_mblaze_fsl_necget>;
|
||||
def NECAGET : FSLGet<0x1B, 0x1B, "necaget ", int_mblaze_fsl_necaget>;
|
||||
def TGET : FSLGet<0x1B, 0x04, "tget ", int_mblaze_fsl_tget>;
|
||||
def TAGET : FSLGet<0x1B, 0x06, "taget ", int_mblaze_fsl_taget>;
|
||||
def TCGET : FSLGet<0x1B, 0x0C, "tcget ", int_mblaze_fsl_tcget>;
|
||||
@ -131,14 +123,25 @@ def TEGET : FSLGet<0x1B, 0x05, "teget ", int_mblaze_fsl_teget>;
|
||||
def TEAGET : FSLGet<0x1B, 0x07, "teaget ", int_mblaze_fsl_teaget>;
|
||||
def TECGET : FSLGet<0x1B, 0x0D, "tecget ", int_mblaze_fsl_tecget>;
|
||||
def TECAGET : FSLGet<0x1B, 0x0F, "tecaget ", int_mblaze_fsl_tecaget>;
|
||||
def TNGET : FSLGet<0x1B, 0x14, "tnget ", int_mblaze_fsl_tnget>;
|
||||
def TNAGET : FSLGet<0x1B, 0x16, "tnaget ", int_mblaze_fsl_tnaget>;
|
||||
def TNCGET : FSLGet<0x1B, 0x1C, "tncget ", int_mblaze_fsl_tncget>;
|
||||
def TNCAGET : FSLGet<0x1B, 0x1E, "tncaget ", int_mblaze_fsl_tncaget>;
|
||||
def TNEGET : FSLGet<0x1B, 0x15, "tneget ", int_mblaze_fsl_tneget>;
|
||||
def TNEAGET : FSLGet<0x1B, 0x17, "tneaget ", int_mblaze_fsl_tneaget>;
|
||||
def TNECGET : FSLGet<0x1B, 0x1D, "tnecget ", int_mblaze_fsl_tnecget>;
|
||||
def TNECAGET : FSLGet<0x1B, 0x1F, "tnecaget ", int_mblaze_fsl_tnecaget>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def NGET : FSLGet<0x1B, 0x10, "nget ", int_mblaze_fsl_nget>;
|
||||
def NAGET : FSLGet<0x1B, 0x12, "naget ", int_mblaze_fsl_naget>;
|
||||
def NCGET : FSLGet<0x1B, 0x18, "ncget ", int_mblaze_fsl_ncget>;
|
||||
def NCAGET : FSLGet<0x1B, 0x1A, "ncaget ", int_mblaze_fsl_ncaget>;
|
||||
def NEGET : FSLGet<0x1B, 0x11, "neget ", int_mblaze_fsl_neget>;
|
||||
def NEAGET : FSLGet<0x1B, 0x13, "neaget ", int_mblaze_fsl_neaget>;
|
||||
def NECGET : FSLGet<0x1B, 0x19, "necget ", int_mblaze_fsl_necget>;
|
||||
def NECAGET : FSLGet<0x1B, 0x1B, "necaget ", int_mblaze_fsl_necaget>;
|
||||
def TNGET : FSLGet<0x1B, 0x14, "tnget ", int_mblaze_fsl_tnget>;
|
||||
def TNAGET : FSLGet<0x1B, 0x16, "tnaget ", int_mblaze_fsl_tnaget>;
|
||||
def TNCGET : FSLGet<0x1B, 0x1C, "tncget ", int_mblaze_fsl_tncget>;
|
||||
def TNCAGET : FSLGet<0x1B, 0x1E, "tncaget ", int_mblaze_fsl_tncaget>;
|
||||
def TNEGET : FSLGet<0x1B, 0x15, "tneget ", int_mblaze_fsl_tneget>;
|
||||
def TNEAGET : FSLGet<0x1B, 0x17, "tneaget ", int_mblaze_fsl_tneaget>;
|
||||
def TNECGET : FSLGet<0x1B, 0x1D, "tnecget ", int_mblaze_fsl_tnecget>;
|
||||
def TNECAGET : FSLGet<0x1B, 0x1F, "tnecaget ", int_mblaze_fsl_tnecaget>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FSL Dynamic Get Instructions
|
||||
@ -151,14 +154,6 @@ def EGETD : FSLGetD<0x13, 0x01, "egetd ", int_mblaze_fsl_eget>;
|
||||
def EAGETD : FSLGetD<0x13, 0x03, "eagetd ", int_mblaze_fsl_eaget>;
|
||||
def ECGETD : FSLGetD<0x13, 0x09, "ecgetd ", int_mblaze_fsl_ecget>;
|
||||
def ECAGETD : FSLGetD<0x13, 0x0B, "ecagetd ", int_mblaze_fsl_ecaget>;
|
||||
def NGETD : FSLGetD<0x13, 0x10, "ngetd ", int_mblaze_fsl_nget>;
|
||||
def NAGETD : FSLGetD<0x13, 0x12, "nagetd ", int_mblaze_fsl_naget>;
|
||||
def NCGETD : FSLGetD<0x13, 0x18, "ncgetd ", int_mblaze_fsl_ncget>;
|
||||
def NCAGETD : FSLGetD<0x13, 0x1A, "ncagetd ", int_mblaze_fsl_ncaget>;
|
||||
def NEGETD : FSLGetD<0x13, 0x11, "negetd ", int_mblaze_fsl_neget>;
|
||||
def NEAGETD : FSLGetD<0x13, 0x13, "neagetd ", int_mblaze_fsl_neaget>;
|
||||
def NECGETD : FSLGetD<0x13, 0x19, "necgetd ", int_mblaze_fsl_necget>;
|
||||
def NECAGETD : FSLGetD<0x13, 0x1B, "necagetd ", int_mblaze_fsl_necaget>;
|
||||
def TGETD : FSLGetD<0x13, 0x04, "tgetd ", int_mblaze_fsl_tget>;
|
||||
def TAGETD : FSLGetD<0x13, 0x06, "tagetd ", int_mblaze_fsl_taget>;
|
||||
def TCGETD : FSLGetD<0x13, 0x0C, "tcgetd ", int_mblaze_fsl_tcget>;
|
||||
@ -167,14 +162,25 @@ def TEGETD : FSLGetD<0x13, 0x05, "tegetd ", int_mblaze_fsl_teget>;
|
||||
def TEAGETD : FSLGetD<0x13, 0x07, "teagetd ", int_mblaze_fsl_teaget>;
|
||||
def TECGETD : FSLGetD<0x13, 0x0D, "tecgetd ", int_mblaze_fsl_tecget>;
|
||||
def TECAGETD : FSLGetD<0x13, 0x0F, "tecagetd ", int_mblaze_fsl_tecaget>;
|
||||
def TNGETD : FSLGetD<0x13, 0x14, "tngetd ", int_mblaze_fsl_tnget>;
|
||||
def TNAGETD : FSLGetD<0x13, 0x16, "tnagetd ", int_mblaze_fsl_tnaget>;
|
||||
def TNCGETD : FSLGetD<0x13, 0x1C, "tncgetd ", int_mblaze_fsl_tncget>;
|
||||
def TNCAGETD : FSLGetD<0x13, 0x1E, "tncagetd ", int_mblaze_fsl_tncaget>;
|
||||
def TNEGETD : FSLGetD<0x13, 0x15, "tnegetd ", int_mblaze_fsl_tneget>;
|
||||
def TNEAGETD : FSLGetD<0x13, 0x17, "tneagetd ", int_mblaze_fsl_tneaget>;
|
||||
def TNECGETD : FSLGetD<0x13, 0x1D, "tnecgetd ", int_mblaze_fsl_tnecget>;
|
||||
def TNECAGETD : FSLGetD<0x13, 0x1F, "tnecagetd", int_mblaze_fsl_tnecaget>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def NGETD : FSLGetD<0x13, 0x10, "ngetd ", int_mblaze_fsl_nget>;
|
||||
def NAGETD : FSLGetD<0x13, 0x12, "nagetd ", int_mblaze_fsl_naget>;
|
||||
def NCGETD : FSLGetD<0x13, 0x18, "ncgetd ", int_mblaze_fsl_ncget>;
|
||||
def NCAGETD : FSLGetD<0x13, 0x1A, "ncagetd ", int_mblaze_fsl_ncaget>;
|
||||
def NEGETD : FSLGetD<0x13, 0x11, "negetd ", int_mblaze_fsl_neget>;
|
||||
def NEAGETD : FSLGetD<0x13, 0x13, "neagetd ", int_mblaze_fsl_neaget>;
|
||||
def NECGETD : FSLGetD<0x13, 0x19, "necgetd ", int_mblaze_fsl_necget>;
|
||||
def NECAGETD : FSLGetD<0x13, 0x1B, "necagetd ", int_mblaze_fsl_necaget>;
|
||||
def TNGETD : FSLGetD<0x13, 0x14, "tngetd ", int_mblaze_fsl_tnget>;
|
||||
def TNAGETD : FSLGetD<0x13, 0x16, "tnagetd ", int_mblaze_fsl_tnaget>;
|
||||
def TNCGETD : FSLGetD<0x13, 0x1C, "tncgetd ", int_mblaze_fsl_tncget>;
|
||||
def TNCAGETD : FSLGetD<0x13, 0x1E, "tncagetd ", int_mblaze_fsl_tncaget>;
|
||||
def TNEGETD : FSLGetD<0x13, 0x15, "tnegetd ", int_mblaze_fsl_tneget>;
|
||||
def TNEAGETD : FSLGetD<0x13, 0x17, "tneagetd ", int_mblaze_fsl_tneaget>;
|
||||
def TNECGETD : FSLGetD<0x13, 0x1D, "tnecgetd ", int_mblaze_fsl_tnecget>;
|
||||
def TNECAGETD : FSLGetD<0x13, 0x1F, "tnecagetd", int_mblaze_fsl_tnecaget>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FSL Put Instructions
|
||||
@ -183,18 +189,21 @@ def PUT : FSLPut<0x1B, 0x0, "put ", int_mblaze_fsl_put>;
|
||||
def APUT : FSLPut<0x1B, 0x1, "aput ", int_mblaze_fsl_aput>;
|
||||
def CPUT : FSLPut<0x1B, 0x4, "cput ", int_mblaze_fsl_cput>;
|
||||
def CAPUT : FSLPut<0x1B, 0x5, "caput ", int_mblaze_fsl_caput>;
|
||||
def NPUT : FSLPut<0x1B, 0x8, "nput ", int_mblaze_fsl_nput>;
|
||||
def NAPUT : FSLPut<0x1B, 0x9, "naput ", int_mblaze_fsl_naput>;
|
||||
def NCPUT : FSLPut<0x1B, 0xC, "ncput ", int_mblaze_fsl_ncput>;
|
||||
def NCAPUT : FSLPut<0x1B, 0xD, "ncaput ", int_mblaze_fsl_ncaput>;
|
||||
def TPUT : FSLPutT<0x1B, 0x2, "tput ", int_mblaze_fsl_tput>;
|
||||
def TAPUT : FSLPutT<0x1B, 0x3, "taput ", int_mblaze_fsl_taput>;
|
||||
def TCPUT : FSLPutT<0x1B, 0x6, "tcput ", int_mblaze_fsl_tcput>;
|
||||
def TCAPUT : FSLPutT<0x1B, 0x7, "tcaput ", int_mblaze_fsl_tcaput>;
|
||||
def TNPUT : FSLPutT<0x1B, 0xA, "tnput ", int_mblaze_fsl_tnput>;
|
||||
def TNAPUT : FSLPutT<0x1B, 0xB, "tnaput ", int_mblaze_fsl_tnaput>;
|
||||
def TNCPUT : FSLPutT<0x1B, 0xE, "tncput ", int_mblaze_fsl_tncput>;
|
||||
def TNCAPUT : FSLPutT<0x1B, 0xF, "tncaput ", int_mblaze_fsl_tncaput>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def NPUT : FSLPut<0x1B, 0x8, "nput ", int_mblaze_fsl_nput>;
|
||||
def NAPUT : FSLPut<0x1B, 0x9, "naput ", int_mblaze_fsl_naput>;
|
||||
def NCPUT : FSLPut<0x1B, 0xC, "ncput ", int_mblaze_fsl_ncput>;
|
||||
def NCAPUT : FSLPut<0x1B, 0xD, "ncaput ", int_mblaze_fsl_ncaput>;
|
||||
def TNPUT : FSLPutT<0x1B, 0xA, "tnput ", int_mblaze_fsl_tnput>;
|
||||
def TNAPUT : FSLPutT<0x1B, 0xB, "tnaput ", int_mblaze_fsl_tnaput>;
|
||||
def TNCPUT : FSLPutT<0x1B, 0xE, "tncput ", int_mblaze_fsl_tncput>;
|
||||
def TNCAPUT : FSLPutT<0x1B, 0xF, "tncaput ", int_mblaze_fsl_tncaput>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FSL Dynamic Put Instructions
|
||||
@ -203,15 +212,18 @@ def PUTD : FSLPutD<0x13, 0x0, "putd ", int_mblaze_fsl_put>;
|
||||
def APUTD : FSLPutD<0x13, 0x1, "aputd ", int_mblaze_fsl_aput>;
|
||||
def CPUTD : FSLPutD<0x13, 0x4, "cputd ", int_mblaze_fsl_cput>;
|
||||
def CAPUTD : FSLPutD<0x13, 0x5, "caputd ", int_mblaze_fsl_caput>;
|
||||
def NPUTD : FSLPutD<0x13, 0x8, "nputd ", int_mblaze_fsl_nput>;
|
||||
def NAPUTD : FSLPutD<0x13, 0x9, "naputd ", int_mblaze_fsl_naput>;
|
||||
def NCPUTD : FSLPutD<0x13, 0xC, "ncputd ", int_mblaze_fsl_ncput>;
|
||||
def NCAPUTD : FSLPutD<0x13, 0xD, "ncaputd ", int_mblaze_fsl_ncaput>;
|
||||
def TPUTD : FSLPutTD<0x13, 0x2, "tputd ", int_mblaze_fsl_tput>;
|
||||
def TAPUTD : FSLPutTD<0x13, 0x3, "taputd ", int_mblaze_fsl_taput>;
|
||||
def TCPUTD : FSLPutTD<0x13, 0x6, "tcputd ", int_mblaze_fsl_tcput>;
|
||||
def TCAPUTD : FSLPutTD<0x13, 0x7, "tcaputd ", int_mblaze_fsl_tcaput>;
|
||||
def TNPUTD : FSLPutTD<0x13, 0xA, "tnputd ", int_mblaze_fsl_tnput>;
|
||||
def TNAPUTD : FSLPutTD<0x13, 0xB, "tnaputd ", int_mblaze_fsl_tnaput>;
|
||||
def TNCPUTD : FSLPutTD<0x13, 0xE, "tncputd ", int_mblaze_fsl_tncput>;
|
||||
def TNCAPUTD : FSLPutTD<0x13, 0xF, "tncaputd ", int_mblaze_fsl_tncaput>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def NPUTD : FSLPutD<0x13, 0x8, "nputd ", int_mblaze_fsl_nput>;
|
||||
def NAPUTD : FSLPutD<0x13, 0x9, "naputd ", int_mblaze_fsl_naput>;
|
||||
def NCPUTD : FSLPutD<0x13, 0xC, "ncputd ", int_mblaze_fsl_ncput>;
|
||||
def NCAPUTD : FSLPutD<0x13, 0xD, "ncaputd ", int_mblaze_fsl_ncaput>;
|
||||
def TNPUTD : FSLPutTD<0x13, 0xA, "tnputd ", int_mblaze_fsl_tnput>;
|
||||
def TNAPUTD : FSLPutTD<0x13, 0xB, "tnaputd ", int_mblaze_fsl_tnaput>;
|
||||
def TNCPUTD : FSLPutTD<0x13, 0xE, "tncputd ", int_mblaze_fsl_tncput>;
|
||||
def TNCAPUTD : FSLPutTD<0x13, 0xF, "tncaputd ", int_mblaze_fsl_tncaput>;
|
||||
}
|
||||
|
||||
@ -330,26 +330,44 @@ class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isCommutable = 1, isAsCheapAsAMove = 1 in {
|
||||
def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>;
|
||||
def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
|
||||
def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>;
|
||||
def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
|
||||
def AND : Logic<0x21, 0x000, "and ", and>;
|
||||
def OR : Logic<0x20, 0x000, "or ", or>;
|
||||
def XOR : Logic<0x22, 0x000, "xor ", xor>;
|
||||
def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
|
||||
def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">;
|
||||
def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>;
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
|
||||
}
|
||||
}
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
|
||||
}
|
||||
}
|
||||
|
||||
let isAsCheapAsAMove = 1 in {
|
||||
def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
|
||||
def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
|
||||
def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
|
||||
def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>;
|
||||
def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
|
||||
def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>;
|
||||
def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>;
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
|
||||
}
|
||||
}
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
|
||||
}
|
||||
}
|
||||
|
||||
let isCommutable = 1, Predicates=[HasMul] in {
|
||||
@ -384,18 +402,27 @@ let Predicates=[HasDiv] in {
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isAsCheapAsAMove = 1 in {
|
||||
def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>;
|
||||
def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>;
|
||||
def ADDIK : ArithI<0x0C, "addik ", add, simm16, immSExt16>;
|
||||
def ADDIKC : ArithNI<0x0E, "addikc ", simm16, immSExt16>;
|
||||
def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>;
|
||||
def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>;
|
||||
def RSUBIK : ArithRI<0x0D, "rsubik ", sub, simm16, immSExt16>;
|
||||
def RSUBIKC : ArithRNI<0x0F, "rsubikc", simm16, immSExt16>;
|
||||
def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>;
|
||||
def ANDI : LogicI<0x29, "andi ", and>;
|
||||
def ORI : LogicI<0x28, "ori ", or>;
|
||||
def XORI : LogicI<0x2A, "xori ", xor>;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>;
|
||||
def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>;
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>;
|
||||
def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>;
|
||||
}
|
||||
}
|
||||
|
||||
let Uses = [CARRY] in {
|
||||
def ADDIKC : ArithNI<0x0E, "addikc ", simm16, immSExt16>;
|
||||
def RSUBIKC : ArithRNI<0x0F, "rsubikc", simm16, immSExt16>;
|
||||
}
|
||||
}
|
||||
|
||||
let Predicates=[HasMul] in {
|
||||
@ -415,26 +442,32 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
||||
|
||||
def LW : LoadM<0x32, 0x000, "lw ">;
|
||||
def LWR : LoadM<0x32, 0x200, "lwr ">;
|
||||
def LWX : LoadM<0x32, 0x400, "lwx ">;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def LWX : LoadM<0x32, 0x400, "lwx ">;
|
||||
}
|
||||
|
||||
def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
|
||||
def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
|
||||
def LWI : LoadMI<0x3A, "lwi ", load>;
|
||||
}
|
||||
|
||||
def SB : StoreM<0x34, 0x000, "sb ">;
|
||||
def SBR : StoreM<0x34, 0x200, "sbr ">;
|
||||
def SB : StoreM<0x34, 0x000, "sb ">;
|
||||
def SBR : StoreM<0x34, 0x200, "sbr ">;
|
||||
|
||||
def SH : StoreM<0x35, 0x000, "sh ">;
|
||||
def SHR : StoreM<0x35, 0x200, "shr ">;
|
||||
def SH : StoreM<0x35, 0x000, "sh ">;
|
||||
def SHR : StoreM<0x35, 0x200, "shr ">;
|
||||
|
||||
def SW : StoreM<0x36, 0x000, "sw ">;
|
||||
def SWR : StoreM<0x36, 0x200, "swr ">;
|
||||
def SW : StoreM<0x36, 0x000, "sw ">;
|
||||
def SWR : StoreM<0x36, 0x200, "swr ">;
|
||||
|
||||
let Defs = [CARRY] in {
|
||||
def SWX : StoreM<0x36, 0x400, "swx ">;
|
||||
}
|
||||
|
||||
def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
|
||||
def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
|
||||
def SWI : StoreMI<0x3E, "swi ", store>;
|
||||
def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
|
||||
def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
|
||||
def SWI : StoreMI<0x3E, "swi ", store>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MBlaze branch instructions
|
||||
@ -501,21 +534,21 @@ let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
|
||||
}
|
||||
|
||||
let isCall =1, hasDelaySlot = 1,
|
||||
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
|
||||
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,CARRY],
|
||||
Uses = [R1] in {
|
||||
def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
|
||||
def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
|
||||
}
|
||||
|
||||
let isCall = 1, hasDelaySlot = 1,
|
||||
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
|
||||
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,CARRY],
|
||||
Uses = [R1] in {
|
||||
def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
|
||||
def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
|
||||
}
|
||||
|
||||
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
hasCtrlDep=1, rd=0x10, Form=FCRI in {
|
||||
rd=0x10, Form=FCRI in {
|
||||
def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
|
||||
"rtsd $target, $imm",
|
||||
[],
|
||||
@ -523,7 +556,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
}
|
||||
|
||||
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
hasCtrlDep=1, rd=0x11, Form=FCRI in {
|
||||
rd=0x11, Form=FCRI in {
|
||||
def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
|
||||
"rtid $target, $imm",
|
||||
[],
|
||||
@ -531,7 +564,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
}
|
||||
|
||||
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
hasCtrlDep=1, rd=0x12, Form=FCRI in {
|
||||
rd=0x12, Form=FCRI in {
|
||||
def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
|
||||
"rtbd $target, $imm",
|
||||
[],
|
||||
@ -539,7 +572,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
}
|
||||
|
||||
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
||||
hasCtrlDep=1, rd=0x14, Form=FCRI in {
|
||||
rd=0x14, Form=FCRI in {
|
||||
def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
|
||||
"rted $target, $imm",
|
||||
[],
|
||||
@ -576,18 +609,21 @@ let usesCustomInserter = 1 in {
|
||||
[]>;
|
||||
}
|
||||
|
||||
|
||||
let rb = 0 in {
|
||||
def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src),
|
||||
"sext16 $dst, $src", [], IIAlu>;
|
||||
def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src),
|
||||
"sext8 $dst, $src", [], IIAlu>;
|
||||
def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
|
||||
"srl $dst, $src", [], IIAlu>;
|
||||
def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
|
||||
"sra $dst, $src", [], IIAlu>;
|
||||
def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
|
||||
"src $dst, $src", [], IIAlu>;
|
||||
let Defs = [CARRY] in {
|
||||
def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
|
||||
"srl $dst, $src", [], IIAlu>;
|
||||
def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
|
||||
"sra $dst, $src", [], IIAlu>;
|
||||
let Uses = [CARRY] in {
|
||||
def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
|
||||
"src $dst, $src", [], IIAlu>;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let isCodeGenOnly=1 in {
|
||||
|
||||
@ -97,6 +97,11 @@ let Namespace = "MBlaze" in {
|
||||
def RPVR9 : MBlazeSPRReg<0x2009, "rpvr9">, DwarfRegNum<[53]>;
|
||||
def RPVR10 : MBlazeSPRReg<0x200A, "rpvr10">, DwarfRegNum<[54]>;
|
||||
def RPVR11 : MBlazeSPRReg<0x200B, "rpvr11">, DwarfRegNum<[55]>;
|
||||
|
||||
// The carry bit. In the Microblaze this is really bit 29 of the
|
||||
// MSR register but this is the only bit of that register that we
|
||||
// are interested in modeling.
|
||||
def CARRY : MBlazeSPRReg<0x0000, "rmsr[c]">, DwarfRegNum<[33]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -179,3 +184,7 @@ def SPR : RegisterClass<"MBlaze", [i32], 32,
|
||||
}
|
||||
}];
|
||||
}
|
||||
|
||||
def CRC : RegisterClass<"MBlaze", [i32], 32, [CARRY]> {
|
||||
let CopyCost = -1;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user