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[Hexagon] Don't call getNumImplicitDefs and then iterate over the count. getNumImplicitDefs contains a loop so its better to just loop over the null terminated implicit def list. NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254852 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-12-05 17:34:07 +00:00
parent b2387dc751
commit 5fa397629b
1 changed files with 25 additions and 24 deletions
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49
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
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@ -85,32 +85,33 @@ void HexagonMCChecker::init(MCInst const& MCI) {
} }
// Get implicit register definitions. // Get implicit register definitions.
const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) { for (; *ImpDef; ++ImpDef) {
unsigned R = ImpDefs[i]; unsigned R = *ImpDef;
if (Hexagon::R31 != R && MCID.isCall()) if (Hexagon::R31 != R && MCID.isCall())
// Any register other than the LR and the PC are actually volatile ones // Any register other than the LR and the PC are actually volatile ones
// as defined by the ABI, not modified implicitly by the call insn. // as defined by the ABI, not modified implicitly by the call insn.
continue; continue;
if (Hexagon::PC == R) if (Hexagon::PC == R)
// Branches are the only insns that can change the PC, // Branches are the only insns that can change the PC,
// otherwise a read-only register. // otherwise a read-only register.
continue; continue;
if (Hexagon::USR_OVF == R) if (Hexagon::USR_OVF == R)
// Many insns change the USR implicitly, but only one or another flag. // Many insns change the USR implicitly, but only one or another flag.
// The instruction table models the USR.OVF flag, which can be implicitly // The instruction table models the USR.OVF flag, which can be implicitly
// modified more than once, but cannot be modified in the same packet // modified more than once, but cannot be modified in the same packet
// with an instruction that modifies is explicitly. Deal with such situ- // with an instruction that modifies is explicitly. Deal with such situ-
// ations individually. // ations individually.
SoftDefs.insert(R); SoftDefs.insert(R);
else if (isPredicateRegister(R) && HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) else if (isPredicateRegister(R) &&
// Include implicit late predicates. HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
LatePreds.insert(R); // Include implicit late predicates.
else LatePreds.insert(R);
Defs[R].insert(PredSense(PredReg, isTrue)); else
} Defs[R].insert(PredSense(PredReg, isTrue));
}
// Figure out explicit register definitions. // Figure out explicit register definitions.
for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {