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AMDGPU: Add subtarget feature for instruction rates

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258085 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2016-01-18 21:13:50 +00:00
parent 1095859c7b
commit 5fc0b0f07e
4 changed files with 23 additions and 9 deletions
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6
lib/Target/AMDGPU/AMDGPU.td
View File

@ -59,6 +59,12 @@ def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
"Assuming f32 fma is at least as fast as mul + add",
[]>;
def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
"HalfRate64Ops",
"true",
"Most fp64 instructions are half rate instead of quarter",
[]>;
// Some instructions do not support denormals despite this flag. Using
// fp32 denormals also causes instructions to run at the double
// precision rate for the device.

11
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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@ -70,11 +70,14 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
DumpCode(false), R600ALUInst(false), HasVertexCache(false),
TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
CaymanISA(false), FlatAddressSpace(false), FlatForGlobal(false),
EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false),
FlatForGlobal(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false),
EnableIfCvt(true), EnableLoadStoreOpt(false),
EnableUnsafeDSOffsetFolding(false),
EnableXNACK(false),
WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
WavefrontSize(0), CFALUBug(false),
LocalMemorySize(0),
EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),

5
lib/Target/AMDGPU/AMDGPUSubtarget.h
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@ -69,6 +69,7 @@ private:
bool FP64Denormals;
bool FP32Denormals;
bool FastFMAF32;
bool HalfRate64Ops;
bool CaymanISA;
bool FlatAddressSpace;
bool FlatForGlobal;
@ -158,6 +159,10 @@ public:
return FastFMAF32;
}
bool hasHalfRate64Ops() const {
return HalfRate64Ops;
}
bool hasFlatAddressSpace() const {
return FlatAddressSpace;
}

10
lib/Target/AMDGPU/Processors.td
View File

@ -84,11 +84,11 @@ def : Proc<"cayman", R600_VLIW4_Itin,
//===----------------------------------------------------------------------===//
def : ProcessorModel<"SI", SIFullSpeedModel,
[FeatureSouthernIslands, FeatureFastFMAF32]
[FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
>;
def : ProcessorModel<"tahiti", SIFullSpeedModel,
[FeatureSouthernIslands, FeatureFastFMAF32]
def : ProcessorModel<"tahiti", SIFullSpeedModel,
[FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
>;
def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
@ -116,8 +116,8 @@ def : ProcessorModel<"kaveri", SIQuarterSpeedModel,
>;
def : ProcessorModel<"hawaii", SIFullSpeedModel,
[FeatureSeaIslands, FeatureFastFMAF32, FeatureLDSBankCount32,
FeatureISAVersion7_0_1]
[FeatureSeaIslands, FeatureFastFMAF32, HalfRate64Ops,
FeatureLDSBankCount32, FeatureISAVersion7_0_1]
>;
def : ProcessorModel<"mullins", SIQuarterSpeedModel,