From 6099306cec808d4a561cf5d337ec83c501a64c92 Mon Sep 17 00:00:00 2001 From: Christian Pirker Date: Tue, 20 May 2014 09:24:37 +0000 Subject: [PATCH] ARMEB: Additional test files for ARM fixups git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209200 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 5 +- test/MC/ARM/big-endian-arm-fixup.s | 107 ++++++++++++++++++ test/MC/ARM/big-endian-thumb-fixup.s | 63 +++++++++++ test/MC/ARM/big-endian-thumb2-fixup.s | 49 ++++++++ 4 files changed, 223 insertions(+), 1 deletion(-) create mode 100644 test/MC/ARM/big-endian-arm-fixup.s create mode 100644 test/MC/ARM/big-endian-thumb-fixup.s create mode 100644 test/MC/ARM/big-endian-thumb2-fixup.s diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 93ec46df07f..7acd9cc4d30 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -742,8 +742,11 @@ void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, // Used to point to big endian bytes. unsigned FullSizeBytes; - if (!IsLittleEndian) + if (!IsLittleEndian) { FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); + assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); + assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); + } // For each byte of the fragment that the fixup touches, mask in the bits from // the fixup value. The Value has been "split up" into the appropriate diff --git a/test/MC/ARM/big-endian-arm-fixup.s b/test/MC/ARM/big-endian-arm-fixup.s new file mode 100644 index 00000000000..5fb9cef5028 --- /dev/null +++ b/test/MC/ARM/big-endian-arm-fixup.s @@ -0,0 +1,107 @@ +// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + .code 32 + +@ARM::fixup_arm_condbl +.section s_condbl,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbl +// CHECK: 0000 0b000002 + bleq condbl_label+16 +condbl_label: + +@ARM::fixup_arm_uncondbl +.section s_uncondbl,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbl +// CHECK: 0000 eb000002 + bl uncond_label+16 +uncond_label: + +@ARM::fixup_arm_blx +.section s_blx,"ax",%progbits +// CHECK-LABEL: Contents of section s_blx +// CHECK: 0000 fa000002 + blx blx_label+16 +blx_label: + +@ARM::fixup_arm_uncondbranch +.section s_uncondbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbranch +// CHECK: 0000 ea000003 + b uncondbranch_label+16 +uncondbranch_label: + +@ARM::fixup_arm_condbranch +.section s_condbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbranch +// CHECK: 0000 0a000003 + beq condbranch_label+16 +condbranch_label: + +@ARM::fixup_arm_pcrel_10 +.section s_arm_pcrel_10,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_pcrel_10 +// CHECK: 0000 ed9f0b03 + vldr d0, arm_pcrel_10_label+16 +arm_pcrel_10_label: + +@ARM::fixup_arm_ldst_pcrel_12 +.section s_arm_ldst_pcrel_12,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_ldst_pcrel_12 +// CHECK: 0000 e59f000c + ldr r0, arm_ldst_pcrel_12_label+16 +arm_ldst_pcrel_12_label: + +@ARM::fixup_arm_adr_pcrel_12 +.section s_arm_adr_pcrel_12,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_adr_pcrel_12 +// CHECK: 0000 e28f0010 + adr r0, arm_adr_pcrel_12_label+20 +arm_adr_pcrel_12_label: + +@ARM::fixup_arm_adr_pcrel_10_unscaled +.section s_arm_adr_pcrel_10_unscaled,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_adr_pcrel_10_unscaled +// CHECK: 0000 e1cf01d4 + ldrd r0, r1, arm_adr_pcrel_10_unscaled_label+24 +arm_adr_pcrel_10_unscaled_label: + +@ARM::fixup_arm_movw_lo16 +.section s_movw,"ax",%progbits +// CHECK-LABEL: Contents of section s_movw +// CHECK: 0000 e3000008 + movw r0, :lower16:(some_label+8) + +@ARM::fixup_arm_movt_hi16 +.section s_movt,"ax",%progbits +// CHECK-LABEL: Contents of section s_movt +// CHECK: 0000 e34f0ffc + movt r0, :upper16:GOT-(movt_label) +movt_label: + +@FK_Data_1 +.section s_fk_data_1 +// CHECK-LABEL: Contents of section s_fk_data_1 +// CHECK: 0000 01 +fk_data1_l_label: +.byte fk_data1_h_label-fk_data1_l_label +fk_data1_h_label: + +@FK_Data_2 +.section s_fk_data_2 +// CHECK-LABEL: Contents of section s_fk_data_2 +// CHECK: 0000 0002 +fk_data2_l_label: +.short fk_data2_h_label-fk_data2_l_label +fk_data2_h_label: + +@FK_Data_4 +.section s_fk_data_4 +// CHECK-LABEL: Contents of section s_fk_data_4 +// CHECK: 0000 00000004 +fk_data4_l_label: +.long fk_data4_h_label-fk_data4_l_label +fk_data4_h_label: + diff --git a/test/MC/ARM/big-endian-thumb-fixup.s b/test/MC/ARM/big-endian-thumb-fixup.s new file mode 100644 index 00000000000..5023fca26be --- /dev/null +++ b/test/MC/ARM/big-endian-thumb-fixup.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + .code 16 + +@ARM::fixup_arm_thumb_bl +.section s_thumb_bl,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_bl +// CHECK: 0000 f000f801 + bl thumb_bl_label + nop +thumb_bl_label: + +@ARM::fixup_arm_thumb_blx +// CHECK-LABEL: Contents of section s_thumb_bl +// CHECK: 0000 f000e802 +.section s_thumb_blx,"ax",%progbits + blx thumb_blx_label+8 +thumb_blx_label: + +@ARM::fixup_arm_thumb_br +.section s_thumb_br,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_br +// CHECK: 0000 e000bf00 + b thumb_br_label + nop +thumb_br_label: + +@ARM::fixup_arm_thumb_bcc +.section s_thumb_bcc,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_bcc +// CHECK: 0000 d000bf00 + beq thumb_bcc_label + nop +thumb_bcc_label: + +@ARM::fixup_arm_thumb_cb +.section s_thumb_cb,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_cb +// CHECK: 0000 b100bf00 + cbz r0, thumb_cb_label + nop +thumb_cb_label: + +@ARM::fixup_arm_thumb_cp +.section s_thumb_cp,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_cp +// CHECK: 0000 4801bf00 + ldr r0, =thumb_cp_label + nop + nop +thumb_cp_label: + +@ARM::fixup_arm_thumb_adr_pcrel_10 +.section s_thumb_adr_pcrel_10,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_adr_pcrel_10 +// CHECK: 0000 a000bf00 + adr r0, thumb_adr_pcrel_10_label + nop +thumb_adr_pcrel_10_label: + diff --git a/test/MC/ARM/big-endian-thumb2-fixup.s b/test/MC/ARM/big-endian-thumb2-fixup.s new file mode 100644 index 00000000000..4fd5276fce6 --- /dev/null +++ b/test/MC/ARM/big-endian-thumb2-fixup.s @@ -0,0 +1,49 @@ +// RUN: llvm-mc -triple=thumbeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + +@ARM::fixup_t2_movw_lo16 +.section s_movw,"ax",%progbits +// CHECK-LABEL: Contents of section s_movw +// CHECK: 0000 f2400008 + movw r0, :lower16:(some_label+8) + +@ARM::fixup_t2_movt_hi16 +.section s_movt,"ax",%progbits +// CHECK-LABEL: Contents of section s_movt +// CHECK: 0000 f6cf70fc + movt r0, :upper16:GOT-(movt_label) +movt_label: + +@ARM::fixup_t2_uncondbranch +.section s_uncondbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbranch +// CHECK: 0000 f000b801 bf00 + b.w uncond_label + nop +uncond_label: + +@ARM::fixup_t2_condbranch +.section s_condbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbranch +// CHECK: 0000 f0008001 bf00 + beq.w cond_label + nop +cond_label: + +@ARM::fixup_t2_ldst_precel_12 +.section s_ldst_precel_12,"ax",%progbits + ldr r0, ldst_precel_12_label + nop + nop +ldst_precel_12_label: + +@ARM::fixup_t2_adr_pcrel_12 +.section s_adr_pcrel_12,"ax",%progbits + adr r0, adr_pcrel_12_label + nop + nop +adr_pcrel_12_label: +