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[X86] Implement the support for shrink-wrapping.
With this patch the x86 backend is now shrink-wrapping capable and this functionality can be tested by using the -enable-shrink-wrap switch. The next step is to make more test and enable shrink-wrapping by default for x86. Related to <rdar://problem/20821487> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
parent
bdfc11784b
commit
60c91c28e4
@ -88,8 +88,9 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
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const bool Uses64BitFramePtr =
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STI->isTarget64BitLP64() || STI->isTargetNaCl64();
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bool UseLEAForSP =
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X86FL->useLEAForSPInProlog(*MBB.getParent());
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// Check if we should use LEA for SP.
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bool UseLEAForSP = STI->useLeaForSP() &&
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X86FL->canUseLEAForSPInEpilogue(*MBB.getParent());
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unsigned StackPtr = TRI->getStackRegister();
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// Check for possible merge with preceding ADD instruction.
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StackAdj += X86FrameLowering::mergeSPUpdates(MBB, MBBI, StackPtr, true);
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@ -565,7 +565,6 @@ static uint64_t calculateMaxStackAlign(const MachineFunction &MF) {
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void X86FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *Fn = MF.getFunction();
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@ -965,15 +964,38 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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bool X86FrameLowering::useLEAForSPInProlog(const MachineFunction &MF) const {
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bool X86FrameLowering::canUseLEAForSPInEpilogue(
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const MachineFunction &MF) const {
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// We can't use LEA instructions for adjusting the stack pointer if this is a
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// leaf function in the Win64 ABI. Only ADD instructions may be used to
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// deallocate the stack.
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// This means that we can use LEA for SP in two situations:
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// 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
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// 2. We *have* a frame pointer which means we are permitted to use LEA.
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return MF.getSubtarget<X86Subtarget>().useLeaForSP() &&
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(!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF));
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return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
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}
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/// Check whether or not the terminators of \p MBB needs to read EFLAGS.
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static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
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for (const MachineInstr &MI : MBB.terminators()) {
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bool BreakNext = false;
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg != X86::EFLAGS)
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continue;
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// This terminator needs an eflag that is not defined
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// by a previous terminator.
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if (!MO.isDef())
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return true;
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BreakNext = true;
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}
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if (BreakNext)
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break;
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}
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return false;
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}
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void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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@ -983,9 +1005,10 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
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const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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assert(MBBI != MBB.end() && "Returning block has no instructions");
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DebugLoc DL = MBBI->getDebugLoc();
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MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
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DebugLoc DL;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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bool Is64Bit = STI.is64Bit();
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// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
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const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
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@ -999,25 +1022,18 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
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bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
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bool UseLEAForSP = useLEAForSPInProlog(MF);
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switch (MBBI->getOpcode()) {
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default:
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llvm_unreachable("Can only insert epilogue into returning blocks");
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case X86::RETQ:
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case X86::RETL:
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case X86::RETIL:
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case X86::RETIQ:
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case X86::TCRETURNdi:
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case X86::TCRETURNri:
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case X86::TCRETURNmi:
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case X86::TCRETURNdi64:
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case X86::TCRETURNri64:
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case X86::TCRETURNmi64:
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case X86::EH_RETURN:
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case X86::EH_RETURN64:
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break; // These are ok
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}
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bool UseLEAForSP = canUseLEAForSPInEpilogue(MF);
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// If we can use LEA for SP but we shouldn't, check that none
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// of the terminators uses the eflags. Otherwise we will insert
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// a ADD that will redefine the eflags and break the condition.
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// Alternatively, we could move the ADD, but this may not be possible
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// and is an optimization anyway.
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if (UseLEAForSP && !MF.getSubtarget<X86Subtarget>().useLeaForSP())
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UseLEAForSP = terminatorsNeedFlagsAsInput(MBB);
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// If that assert breaks, that means we do not do the right thing
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// in canUseAsEpilogue.
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assert((UseLEAForSP || !terminatorsNeedFlagsAsInput(MBB)) &&
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"We shouldn't have allowed this insertion point");
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// Get the number of bytes to allocate from the FrameInfo.
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uint64_t StackSize = MFI->getStackSize();
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@ -1056,7 +1072,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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}
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MachineBasicBlock::iterator FirstCSPop = MBBI;
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DL = MBBI->getDebugLoc();
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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// If there is an ADD32ri or SUB32ri of ESP immediately before this
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// instruction, merge the two instructions.
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@ -1514,8 +1531,6 @@ static const uint64_t kSplitStackAvailable = 256;
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void X86FrameLowering::adjustForSegmentedStacks(
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MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
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assert(&PrologueMBB == &MF.front() &&
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"Shrink-wrapping is not implemented yet");
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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@ -1835,8 +1850,6 @@ void X86FrameLowering::adjustForHiPEPrologue(
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// If the stack frame needed is larger than the guaranteed then runtime checks
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// and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
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if (MaxStack > Guaranteed) {
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assert(&PrologueMBB == &MF.front() &&
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"Shrink-wrapping is not implemented yet");
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MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
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MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
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@ -1979,3 +1992,15 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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}
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}
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bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
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assert(MBB.getParent() && "Block is not attached to a function!");
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if (canUseLEAForSPInEpilogue(*MBB.getParent()))
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return true;
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// If we cannot use LEA to adjust SP, we may need to use ADD, which
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// clobbers the EFLAGS. Check that none of the terminators reads the
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// EFLAGS, and if one uses it, conservatively assume this is not
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// safe to insert the epilogue here.
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return !terminatorsNeedFlagsAsInput(MBB);
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}
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@ -96,8 +96,15 @@ public:
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const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI);
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/// Check that LEA can be use on SP in a prologue sequence for \p MF.
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bool useLEAForSPInProlog(const MachineFunction &MF) const;
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/// Check that LEA can be used on SP in an epilogue sequence for \p MF.
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bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const;
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/// Check whether or not the given \p MBB can be used as a epilogue
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/// for the target.
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/// The epilogue will be inserted before the first terminator of that block.
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/// This method is used by the shrink-wrapping pass to decide if
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/// \p MBB will be correctly handled by the target.
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
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private:
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/// convertArgMovsToPushes - This method tries to convert a call sequence
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600
test/CodeGen/X86/x86-shrink-wrapping.ll
Normal file
600
test/CodeGen/X86/x86-shrink-wrapping.ll
Normal file
@ -0,0 +1,600 @@
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; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
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; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
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;
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; Note: Lots of tests use inline asm instead of regular calls.
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; This allows to have a better control on what the allocation will do.
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; Otherwise, we may have spill right in the entry block, defeating
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; shrink-wrapping. Moreover, some of the inline asm statement (nop)
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; are here to ensure that the related paths do not end up as critical
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; edges.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "x86_64-apple-macosx"
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; Initial motivating example: Simple diamond with a call just on one side.
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; CHECK-LABEL: foo:
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;
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; Compare the arguments and jump to exit.
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; No prologue needed.
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; ENABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
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; ENABLE-NEXT: cmpl %esi, [[ARG0CPY]]
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; ENABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; (What we push does not matter. It should be some random sratch register.)
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; CHECK: pushq
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;
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; Compare the arguments and jump to exit.
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; After the prologue is set.
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; DISABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
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; DISABLE-NEXT: cmpl %esi, [[ARG0CPY]]
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; DISABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Store %a in the alloca.
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; CHECK: movl [[ARG0CPY]], 4(%rsp)
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; Set the alloca address in the second argument.
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; CHECK-NEXT: leaq 4(%rsp), %rsi
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; Set the first argument to zero.
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; CHECK-NEXT: xorl %edi, %edi
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; CHECK-NEXT: callq _doSomething
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;
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; With shrink-wrapping, epilogue is just after the call.
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; ENABLE-NEXT: addq $8, %rsp
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;
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; CHECK: [[EXIT_LABEL]]:
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;
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; Without shrink-wrapping, epilogue is in the exit block.
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; Epilogue code. (What we pop does not matter.)
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; DISABLE-NEXT: popq
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;
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; CHECK-NEXT: retq
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define i32 @foo(i32 %a, i32 %b) {
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%tmp = alloca i32, align 4
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%tmp2 = icmp slt i32 %a, %b
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br i1 %tmp2, label %true, label %false
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true:
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store i32 %a, i32* %tmp, align 4
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%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
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br label %false
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false:
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%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
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ret i32 %tmp.0
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}
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; Function Attrs: optsize
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declare i32 @doSomething(i32, i32*)
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; Check that we do not perform the restore inside the loop whereas the save
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; is outside.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
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;
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; Shrink-wrapping allows to skip the prologue in the else case.
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; ENABLE: testl %edi, %edi
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; ENABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; SUM is in %esi because it is coalesced with the second
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; argument on the else path.
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; CHECK: xorl [[SUM:%esi]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP]]
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;
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; Next BB.
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; SUM << 3.
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; CHECK: shll $3, [[SUM]]
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;
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; Jump to epilogue.
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; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: addl %esi, %esi
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; DISABLE: [[EPILOG_BB]]: ## %if.end
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;
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; Epilogue code.
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; CHECK-DAG: popq %rbx
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; CHECK-DAG: movl %esi, %eax
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; CHECK: retq
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;
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; ENABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: addl %esi, %esi
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; ENABLE-NEXT: movl %esi, %eax
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; ENABLE-NEXT: retq
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define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare i32 @something(...)
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; Check that we do not perform the shrink-wrapping inside the loop even
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; though that would be legal. The cost model must prevent that.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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; CHECK: nop
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; CHECK: xorl [[SUM:%e[a-z]+]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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; Next BB.
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: ## %for.exit
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; CHECK: nop
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; CHECK: popq %rbx
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; CHECK-NEXT: retq
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define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
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entry:
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br label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
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%sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.03
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%inc = add nuw nsw i32 %i.04, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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tail call void asm "nop", ""()
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br label %for.end
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for.end: ; preds = %for.body
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ret i32 %add
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}
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; Check with a more complex case that we do not have save within the loop and
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; restore outside.
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; CHECK-LABEL: loopInfoSaveOutsideLoop:
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;
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; ENABLE: testl %edi, %edi
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; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; CHECK: nop
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; CHECK: xorl [[SUM:%esi]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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;
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
|
||||
; CHECK: movl $1, [[TMP:%e[a-z]+]]
|
||||
; CHECK: addl [[TMP]], [[SUM]]
|
||||
; CHECK-NEXT: decl [[IV]]
|
||||
; CHECK-NEXT: jne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: nop
|
||||
; CHECK: shll $3, [[SUM]]
|
||||
;
|
||||
; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; DISABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; DISABLE: addl %esi, %esi
|
||||
; DISABLE: [[EPILOG_BB]]: ## %if.end
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK-DAG: popq %rbx
|
||||
; CHECK-DAG: movl %esi, %eax
|
||||
; CHECK: retq
|
||||
;
|
||||
; ENABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; ENABLE: addl %esi, %esi
|
||||
; ENABLE-NEXT: movl %esi, %eax
|
||||
; ENABLE-NEXT: retq
|
||||
define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %for.preheader
|
||||
|
||||
for.preheader:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
|
||||
%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
|
||||
%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
|
||||
%add = add nsw i32 %call, %sum.04
|
||||
%inc = add nuw nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.end, label %for.body
|
||||
|
||||
for.end: ; preds = %for.body
|
||||
tail call void asm "nop", "~{ebx}"()
|
||||
%shl = shl i32 %add, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %for.end
|
||||
%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
|
||||
ret i32 %sum.1
|
||||
}
|
||||
|
||||
declare void @somethingElse(...)
|
||||
|
||||
; Check with a more complex case that we do not have restore within the loop and
|
||||
; save outside.
|
||||
; CHECK-LABEL: loopInfoRestoreOutsideLoop:
|
||||
;
|
||||
; ENABLE: testl %edi, %edi
|
||||
; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; Make sure we save the CSR used in the inline asm: rbx.
|
||||
; CHECK: pushq %rbx
|
||||
;
|
||||
; DISABLE: testl %edi, %edi
|
||||
; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: nop
|
||||
; CHECK: xorl [[SUM:%esi]], [[SUM]]
|
||||
; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
|
||||
;
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
|
||||
; CHECK: movl $1, [[TMP:%e[a-z]+]]
|
||||
; CHECK: addl [[TMP]], [[SUM]]
|
||||
; CHECK-NEXT: decl [[IV]]
|
||||
; CHECK-NEXT: jne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: shll $3, [[SUM]]
|
||||
;
|
||||
; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; DISABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
|
||||
; Shift second argument by one and store into returned register.
|
||||
; DISABLE: addl %esi, %esi
|
||||
; DISABLE: [[EPILOG_BB]]: ## %if.end
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK-DAG: popq %rbx
|
||||
; CHECK-DAG: movl %esi, %eax
|
||||
; CHECK: retq
|
||||
;
|
||||
; ENABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; ENABLE: addl %esi, %esi
|
||||
; ENABLE-NEXT: movl %esi, %eax
|
||||
; ENABLE-NEXT: retq
|
||||
define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void asm "nop", "~{ebx}"()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body, %if.then
|
||||
%i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
|
||||
%sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
|
||||
%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
|
||||
%add = add nsw i32 %call, %sum.04
|
||||
%inc = add nuw nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.end, label %for.body
|
||||
|
||||
for.end: ; preds = %for.body
|
||||
%shl = shl i32 %add, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %for.end
|
||||
%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
|
||||
ret i32 %sum.1
|
||||
}
|
||||
|
||||
; Check that we handle function with no frame information correctly.
|
||||
; CHECK-LABEL: emptyFrame:
|
||||
; CHECK: ## %entry
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: retq
|
||||
define i32 @emptyFrame() {
|
||||
entry:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; Check that we handle inline asm correctly.
|
||||
; CHECK-LABEL: inlineAsm:
|
||||
;
|
||||
; ENABLE: testl %edi, %edi
|
||||
; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; Make sure we save the CSR used in the inline asm: rbx.
|
||||
; CHECK: pushq %rbx
|
||||
;
|
||||
; DISABLE: testl %edi, %edi
|
||||
; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: nop
|
||||
; CHECK: movl $10, [[IV:%e[a-z]+]]
|
||||
;
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
|
||||
; Inline asm statement.
|
||||
; CHECK: addl $1, %ebx
|
||||
; CHECK: decl [[IV]]
|
||||
; CHECK-NEXT: jne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: nop
|
||||
; CHECK: xorl %esi, %esi
|
||||
;
|
||||
; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
|
||||
;
|
||||
; DISABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; DISABLE: addl %esi, %esi
|
||||
; DISABLE: [[EPILOG_BB]]: ## %if.end
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK-DAG: popq %rbx
|
||||
; CHECK-DAG: movl %esi, %eax
|
||||
; CHECK: retq
|
||||
;
|
||||
; ENABLE: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; ENABLE: addl %esi, %esi
|
||||
; ENABLE-NEXT: movl %esi, %eax
|
||||
; ENABLE-NEXT: retq
|
||||
define i32 @inlineAsm(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %for.preheader
|
||||
|
||||
for.preheader:
|
||||
tail call void asm "nop", ""()
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
|
||||
tail call void asm "addl $$1, %ebx", "~{ebx}"()
|
||||
%inc = add nuw nsw i32 %i.03, 1
|
||||
%exitcond = icmp eq i32 %inc, 10
|
||||
br i1 %exitcond, label %for.exit, label %for.body
|
||||
|
||||
for.exit:
|
||||
tail call void asm "nop", ""()
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %for.body, %if.else
|
||||
%sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
|
||||
ret i32 %sum.0
|
||||
}
|
||||
|
||||
; Check that we handle calls to variadic functions correctly.
|
||||
; CHECK-LABEL: callVariadicFunc:
|
||||
;
|
||||
; ENABLE: testl %edi, %edi
|
||||
; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Prologue code.
|
||||
; CHECK: pushq
|
||||
;
|
||||
; DISABLE: testl %edi, %edi
|
||||
; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; Setup of the varags.
|
||||
; CHECK: movl %esi, (%rsp)
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: %esi, %edi
|
||||
; CHECK-NEXT: %esi, %edx
|
||||
; CHECK-NEXT: %esi, %r8d
|
||||
; CHECK-NEXT: %esi, %r9d
|
||||
; CHECK-NEXT: %esi, %ecx
|
||||
; CHECK-NEXT: callq _someVariadicFunc
|
||||
; CHECK-NEXT: movl %eax, %esi
|
||||
; CHECK-NEXT: shll $3, %esi
|
||||
;
|
||||
; ENABLE-NEXT: addq $8, %rsp
|
||||
; ENABLE-NEXT: movl %esi, %eax
|
||||
; ENABLE-NEXT: retq
|
||||
;
|
||||
; DISABLE: jmp [[IFEND_LABEL:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: [[ELSE_LABEL]]: ## %if.else
|
||||
; Shift second argument by one and store into returned register.
|
||||
; CHECK: addl %esi, %esi
|
||||
;
|
||||
; DISABLE: [[IFEND_LABEL]]: ## %if.end
|
||||
;
|
||||
; Epilogue code.
|
||||
; CHECK-NEXT: movl %esi, %eax
|
||||
; DISABLE-NEXT: popq
|
||||
; CHECK-NEXT: retq
|
||||
define i32 @callVariadicFunc(i32 %cond, i32 %N) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
|
||||
%shl = shl i32 %call, 3
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%mul = shl nsw i32 %N, 1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
|
||||
ret i32 %sum.0
|
||||
}
|
||||
|
||||
declare i32 @someVariadicFunc(i32, ...)
|
||||
|
||||
; Check that we use LEA not to clobber EFLAGS.
|
||||
%struct.temp_slot = type { %struct.temp_slot*, %struct.rtx_def*, %struct.rtx_def*, i32, i64, %union.tree_node*, %union.tree_node*, i8, i8, i32, i32, i64, i64 }
|
||||
%union.tree_node = type { %struct.tree_decl }
|
||||
%struct.tree_decl = type { %struct.tree_common, i8*, i32, i32, %union.tree_node*, i48, %union.anon, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %union.anon.1, %union.tree_node*, %union.tree_node*, %union.tree_node*, i64, %struct.lang_decl* }
|
||||
%struct.tree_common = type { %union.tree_node*, %union.tree_node*, i32 }
|
||||
%union.anon = type { i64 }
|
||||
%union.anon.1 = type { %struct.function* }
|
||||
%struct.function = type { %struct.eh_status*, %struct.stmt_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, i8*, %union.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.ix86_args, %struct.rtx_def*, %struct.rtx_def*, i8*, %struct.initial_value_struct*, i32, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i64, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.rtx_def**, %struct.temp_slot*, i32, i32, i32, %struct.var_refs_queue*, i32, i32, i8*, %union.tree_node*, %struct.rtx_def*, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.rtx_def*, i24 }
|
||||
%struct.eh_status = type opaque
|
||||
%struct.stmt_status = type opaque
|
||||
%struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
|
||||
%struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack*, i32, i32, i8*, i32, i8*, %union.tree_node**, %struct.rtx_def** }
|
||||
%struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack* }
|
||||
%struct.varasm_status = type opaque
|
||||
%struct.ix86_args = type { i32, i32, i32, i32, i32, i32, i32 }
|
||||
%struct.initial_value_struct = type opaque
|
||||
%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
|
||||
%struct.machine_function = type opaque
|
||||
%struct.language_function = type opaque
|
||||
%struct.lang_decl = type opaque
|
||||
%struct.rtx_def = type { i32, [1 x %union.rtunion_def] }
|
||||
%union.rtunion_def = type { i64 }
|
||||
|
||||
declare hidden fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* readonly)
|
||||
|
||||
; CHECK-LABEL: useLEA:
|
||||
; DISABLE: pushq
|
||||
;
|
||||
; CHECK: testq %rdi, %rdi
|
||||
; CHECK-NEXT: je [[CLEANUP:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: movzwl (%rdi), [[BF_LOAD:%e[a-z]+]]
|
||||
; CHECK-NEXT: cmpl $66, [[BF_LOAD]]
|
||||
; CHECK-NEXT: jne [[CLEANUP]]
|
||||
;
|
||||
; CHECK: movq 8(%rdi), %rdi
|
||||
; CHECK-NEXT: movzwl (%rdi), %e[[BF_LOAD2:[a-z]+]]
|
||||
; CHECK-NEXT: leal -54(%r[[BF_LOAD2]]), [[TMP:%e[a-z]+]]
|
||||
; CHECK-NEXT: cmpl $14, [[TMP]]
|
||||
; CHECK-NEXT: ja [[LOR_LHS_FALSE:LBB[0-9_]+]]
|
||||
;
|
||||
; CHECK: movl $24599, [[TMP2:%e[a-z]+]]
|
||||
; CHECK-NEXT: btl [[TMP]], [[TMP2]]
|
||||
; CHECK-NEXT: jb [[CLEANUP]]
|
||||
;
|
||||
; CHECK: [[LOR_LHS_FALSE]]: ## %lor.lhs.false
|
||||
; CHECK: cmpl $134, %e[[BF_LOAD2]]
|
||||
; CHECK-NEXT: je [[CLEANUP]]
|
||||
;
|
||||
; CHECK: cmpl $140, %e[[BF_LOAD2]]
|
||||
; CHECK-NEXT: je [[CLEANUP]]
|
||||
;
|
||||
; ENABLE: pushq
|
||||
; CHECK: callq _find_temp_slot_from_address
|
||||
; CHECK-NEXT: testq %rax, %rax
|
||||
;
|
||||
; The adjustment must use LEA here (or be moved above the test).
|
||||
; ENABLE-NEXT: leaq 8(%rsp), %rsp
|
||||
;
|
||||
; CHECK-NEXT: je [[CLEANUP]]
|
||||
;
|
||||
; CHECK: movb $1, 57(%rax)
|
||||
;
|
||||
; CHECK: [[CLEANUP]]: ## %cleanup
|
||||
; DISABLE: popq
|
||||
; CHECK-NEXT: retq
|
||||
define void @useLEA(%struct.rtx_def* readonly %x) {
|
||||
entry:
|
||||
%cmp = icmp eq %struct.rtx_def* %x, null
|
||||
br i1 %cmp, label %cleanup, label %if.end
|
||||
|
||||
if.end: ; preds = %entry
|
||||
%tmp = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 0
|
||||
%bf.load = load i32, i32* %tmp, align 8
|
||||
%bf.clear = and i32 %bf.load, 65535
|
||||
%cmp1 = icmp eq i32 %bf.clear, 66
|
||||
br i1 %cmp1, label %lor.lhs.false, label %cleanup
|
||||
|
||||
lor.lhs.false: ; preds = %if.end
|
||||
%arrayidx = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 1, i64 0
|
||||
%rtx = bitcast %union.rtunion_def* %arrayidx to %struct.rtx_def**
|
||||
%tmp1 = load %struct.rtx_def*, %struct.rtx_def** %rtx, align 8
|
||||
%tmp2 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %tmp1, i64 0, i32 0
|
||||
%bf.load2 = load i32, i32* %tmp2, align 8
|
||||
%bf.clear3 = and i32 %bf.load2, 65535
|
||||
switch i32 %bf.clear3, label %if.end.55 [
|
||||
i32 67, label %cleanup
|
||||
i32 68, label %cleanup
|
||||
i32 54, label %cleanup
|
||||
i32 55, label %cleanup
|
||||
i32 58, label %cleanup
|
||||
i32 134, label %cleanup
|
||||
i32 56, label %cleanup
|
||||
i32 140, label %cleanup
|
||||
]
|
||||
|
||||
if.end.55: ; preds = %lor.lhs.false
|
||||
%call = tail call fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* %tmp1) #2
|
||||
%cmp59 = icmp eq %struct.temp_slot* %call, null
|
||||
br i1 %cmp59, label %cleanup, label %if.then.60
|
||||
|
||||
if.then.60: ; preds = %if.end.55
|
||||
%addr_taken = getelementptr inbounds %struct.temp_slot, %struct.temp_slot* %call, i64 0, i32 8
|
||||
store i8 1, i8* %addr_taken, align 1
|
||||
br label %cleanup
|
||||
|
||||
cleanup: ; preds = %if.then.60, %if.end.55, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %if.end, %entry
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user