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[Hexagon] Better handling of HVX vector lowering

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- Expand SELECT_CC and BR_CC for vector types.
- Implement TLI::isShuffleMaskLegal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281397 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-09-13 21:16:07 +00:00
parent 9f45ab58fc
commit 60fc58a44d
3 changed files with 38 additions and 4 deletions
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18
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1981,6 +1981,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SRA, VT, Custom);
setOperationAction(ISD::SHL, VT, Custom);
setOperationAction(ISD::SRL, VT, Custom);
setOperationAction(ISD::BR_CC, VT, Expand);
setOperationAction(ISD::SELECT_CC, VT, Expand);
}
// Types natively supported:
@ -2006,6 +2009,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
if (UseHVX) {
if (UseHVXSgl) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
@ -2299,9 +2303,8 @@ bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
}
// Should we expand the build vector with shuffles?
bool
HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const {
bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const {
// Hexagon vector shuffle operates on element sizes of bytes or halfwords
EVT EltVT = VT.getVectorElementType();
int EltBits = EltVT.getSizeInBits();
@ -2311,7 +2314,7 @@ HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
}
static StridedLoadKind isStridedLoad(ArrayRef<int> &Mask) {
static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
int even_start = -2;
int odd_start = -1;
size_t mask_len = Mask.size();
@ -2335,6 +2338,13 @@ static StridedLoadKind isStridedLoad(ArrayRef<int> &Mask) {
return StridedLoadKind::NoPattern;
}
bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const {
if (Subtarget.useHVXOps())
return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
return true;
}
// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
// to select data from, V3 is the permutation.
SDValue

3
lib/Target/Hexagon/HexagonISelLowering.h
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@ -125,6 +125,9 @@ bool isPositiveHalfWord(SDNode *N);
bool shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;

21
test/CodeGen/Hexagon/build-vector-shuffle.ll Normal file
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@ -0,0 +1,21 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we don't crash.
; CHECK: vshuff
target triple = "hexagon"
define void @hex_interleaved.s0.__outermost() local_unnamed_addr #0 {
entry:
%0 = icmp eq i32 undef, 0
%sel2 = select i1 %0, <32 x i16> undef, <32 x i16> zeroinitializer
%1 = bitcast <32 x i16> %sel2 to <16 x i32>
%2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
store <16 x i32> %2, <16 x i32>* undef, align 2
unreachable
}
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
attributes #1 = { nounwind readnone }