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[x86] Switching the shuffle equivalence test to a variadic template was
the wrong answer. We also got initializer lists which are *way* cleaner for this kind of thing. Let's use those and make this a normal, boring functionn accepting ArrayRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
05e2b94f35
commit
634fc5f26b
@ -5998,57 +5998,39 @@ is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
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return true;
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}
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/// \brief Base case helper for testing a single mask element.
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static bool isShuffleEquivalentImpl(SDValue V1, SDValue V2,
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BuildVectorSDNode *BV1,
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BuildVectorSDNode *BV2, ArrayRef<int> Mask,
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int i, int Arg) {
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int Size = Mask.size();
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if (Mask[i] != -1 && Mask[i] != Arg) {
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auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
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auto *ArgsBV = Arg < Size ? BV1 : BV2;
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if (!MaskBV || !ArgsBV ||
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MaskBV->getOperand(Mask[i] % Size) != ArgsBV->getOperand(Arg % Size))
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return false;
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}
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return true;
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}
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/// \brief Recursive helper to peel off and test each mask element.
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template <typename... Ts>
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static bool isShuffleEquivalentImpl(SDValue V1, SDValue V2,
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BuildVectorSDNode *BV1,
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BuildVectorSDNode *BV2, ArrayRef<int> Mask,
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int i, int Arg, Ts... Args) {
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if (!isShuffleEquivalentImpl(V1, V2, BV1, BV2, Mask, i, Arg))
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return false;
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return isShuffleEquivalentImpl(V1, V2, BV1, BV2, Mask, i + 1, Args...);
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}
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/// \brief Checks whether a shuffle mask is equivalent to an explicit list of
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/// arguments.
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///
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/// This is a fast way to test a shuffle mask against a fixed pattern:
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///
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/// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
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/// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
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///
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/// It returns true if the mask is exactly as wide as the argument list, and
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/// each element of the mask is either -1 (signifying undef) or the value given
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/// in the argument.
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template <typename... Ts>
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static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
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Ts... Args) {
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if (Mask.size() != sizeof...(Args))
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ArrayRef<int> ExpectedMask) {
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if (Mask.size() != ExpectedMask.size())
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return false;
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int Size = Mask.size();
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// If the values are build vectors, we can look through them to find
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// equivalent inputs that make the shuffles equivalent.
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auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
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auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
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// Recursively peel off arguments and test them against the mask.
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return isShuffleEquivalentImpl(V1, V2, BV1, BV2, Mask, 0, Args...);
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for (int i = 0; i < Size; ++i)
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if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
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auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
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auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
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if (!MaskBV || !ExpectedBV ||
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MaskBV->getOperand(Mask[i] % Size) !=
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ExpectedBV->getOperand(ExpectedMask[i] % Size))
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return false;
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}
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return true;
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}
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/// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
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@ -7216,7 +7198,7 @@ static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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if (isSingleInputShuffleMask(Mask)) {
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// Use low duplicate instructions for masks that match their pattern.
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if (Subtarget->hasSSE3())
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if (isShuffleEquivalent(V1, V2, Mask, 0, 0))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
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return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
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// Straight shuffle of a single input vector. Simulate this by using the
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@ -7252,7 +7234,8 @@ static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// Try to use one of the special instruction patterns to handle two common
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// blend patterns if a zero-blend above didn't work.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 3) || isShuffleEquivalent(V1, V2, Mask, 1, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
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isShuffleEquivalent(V1, V2, Mask, {1, 3}))
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if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
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// We can either use a special instruction to load over the low double or
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// to move just the low double.
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@ -7267,9 +7250,9 @@ static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Blend;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
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unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
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@ -7362,9 +7345,9 @@ static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Blend;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
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// Try to use byte rotation instructions.
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@ -7525,9 +7508,9 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// Use even/odd duplicate instructions for masks that match their pattern.
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if (Subtarget->hasSSE3()) {
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if (isShuffleEquivalent(V1, V2, Mask, 0, 0, 2, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
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return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 1, 3, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
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return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
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}
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@ -7570,13 +7553,13 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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}
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 4, 1, 5))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 2, 6, 3, 7))
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if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 4, 0, 5, 1))
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if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 6, 2, 7, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
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// Otherwise fall back to a SHUFPS lowering strategy.
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@ -7621,9 +7604,9 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// so prevents folding a load into this instruction or making a copy.
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const int UnpackLoMask[] = {0, 0, 1, 1};
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const int UnpackHiMask[] = {2, 2, 3, 3};
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if (isShuffleEquivalent(V1, V2, Mask, 0, 0, 1, 1))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
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Mask = UnpackLoMask;
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else if (isShuffleEquivalent(V1, V2, Mask, 2, 2, 3, 3))
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else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
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Mask = UnpackHiMask;
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return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
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@ -7654,13 +7637,13 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Masked;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 4, 1, 5))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 2, 6, 3, 7))
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if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 4, 0, 5, 1))
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if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 6, 2, 7, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
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// Try to use byte rotation instructions.
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@ -7743,9 +7726,9 @@ static SDValue lowerV8I16SingleInputVectorShuffle(
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return Shift;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V, V, Mask, 0, 0, 1, 1, 2, 2, 3, 3))
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if (isShuffleEquivalent(V, V, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
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if (isShuffleEquivalent(V, V, Mask, 4, 4, 5, 5, 6, 6, 7, 7))
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if (isShuffleEquivalent(V, V, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
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// Try to use byte rotation instructions.
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@ -8277,9 +8260,9 @@ static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Masked;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 8, 1, 9, 2, 10, 3, 11))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 4, 12, 5, 13, 6, 14, 7, 15))
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if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
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// Try to use byte rotation instructions.
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@ -8514,13 +8497,15 @@ static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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}
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask,
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0, 16, 1, 17, 2, 18, 3, 19,
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4, 20, 5, 21, 6, 22, 7, 23))
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if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
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0, 16, 1, 17, 2, 18, 3, 19,
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// High half.
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4, 20, 5, 21, 6, 22, 7, 23}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask,
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8, 24, 9, 25, 10, 26, 11, 27,
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12, 28, 13, 29, 14, 30, 15, 31))
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if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
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8, 24, 9, 25, 10, 26, 11, 27,
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// High half.
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12, 28, 13, 29, 14, 30, 15, 31}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
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// Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
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@ -9006,15 +8991,15 @@ static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
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VT.getVectorNumElements() / 2);
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// Check for patterns which can be matched with a single insert of a 128-bit
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// subvector.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 1, 0, 1) ||
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isShuffleEquivalent(V1, V2, Mask, 0, 1, 4, 5)) {
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if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}) ||
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isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
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SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
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DAG.getIntPtrConstant(0));
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SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
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Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
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}
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if (isShuffleEquivalent(V1, V2, Mask, 0, 1, 6, 7)) {
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if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 6, 7})) {
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SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
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DAG.getIntPtrConstant(0));
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SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
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@ -9153,7 +9138,7 @@ static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Broadcast;
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// Use low duplicate instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 0, 2, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
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return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
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if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
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@ -9177,13 +9162,13 @@ static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 4, 2, 6))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 5, 3, 7))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 4, 0, 6, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 5, 1, 7, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
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// If we have a single input to the zero element, insert that into V1 if we
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@ -9299,13 +9284,13 @@ static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Shift;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 4, 2, 6))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 5, 3, 7))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, 4, 0, 6, 2))
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if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 5, 1, 7, 3))
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if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
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// Try to simplify this by merging 128-bit lanes to enable a lane-based
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@ -9354,9 +9339,9 @@ static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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"Repeated masks must be half the mask width!");
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// Use even/odd duplicate instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 0, 2, 2, 4, 4, 6, 6))
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
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return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
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if (isShuffleEquivalent(V1, V2, Mask, 1, 1, 3, 3, 5, 5, 7, 7))
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if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
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return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
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if (isSingleInputShuffleMask(Mask))
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@ -9364,13 +9349,13 @@ static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask, 0, 8, 1, 9, 4, 12, 5, 13))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 2, 10, 3, 11, 6, 14, 7, 15))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 8, 0, 9, 1, 12, 4, 13, 5))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 10, 2, 11, 3, 14, 6, 15, 7))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
|
||||
|
||||
// Otherwise, fall back to a SHUFPS sequence. Here it is important that we
|
||||
@ -9464,13 +9449,13 @@ static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
|
||||
|
||||
// Use dedicated unpack instructions for masks that match their pattern.
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 0, 8, 1, 9, 4, 12, 5, 13))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 2, 10, 3, 11, 6, 14, 7, 15))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 8, 0, 9, 1, 12, 4, 13, 5))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 10, 2, 11, 3, 14, 6, 15, 7))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
|
||||
}
|
||||
|
||||
@ -9539,16 +9524,16 @@ static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
|
||||
// Use dedicated unpack instructions for masks that match their pattern.
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
// First 128-bit lane:
|
||||
0, 16, 1, 17, 2, 18, 3, 19,
|
||||
// Second 128-bit lane:
|
||||
8, 24, 9, 25, 10, 26, 11, 27))
|
||||
{// First 128-bit lane:
|
||||
0, 16, 1, 17, 2, 18, 3, 19,
|
||||
// Second 128-bit lane:
|
||||
8, 24, 9, 25, 10, 26, 11, 27}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
// First 128-bit lane:
|
||||
4, 20, 5, 21, 6, 22, 7, 23,
|
||||
// Second 128-bit lane:
|
||||
12, 28, 13, 29, 14, 30, 15, 31))
|
||||
{// First 128-bit lane:
|
||||
4, 20, 5, 21, 6, 22, 7, 23,
|
||||
// Second 128-bit lane:
|
||||
12, 28, 13, 29, 14, 30, 15, 31}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
|
||||
|
||||
// Try to use shift instructions.
|
||||
@ -9634,17 +9619,17 @@ static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
// 256-bit lanes.
|
||||
if (isShuffleEquivalent(
|
||||
V1, V2, Mask,
|
||||
// First 128-bit lane:
|
||||
0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
|
||||
// Second 128-bit lane:
|
||||
16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
|
||||
{// First 128-bit lane:
|
||||
0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
|
||||
// Second 128-bit lane:
|
||||
16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
|
||||
if (isShuffleEquivalent(
|
||||
V1, V2, Mask,
|
||||
// First 128-bit lane:
|
||||
8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
|
||||
// Second 128-bit lane:
|
||||
24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
|
||||
{// First 128-bit lane:
|
||||
8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
|
||||
// Second 128-bit lane:
|
||||
24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
|
||||
|
||||
// Try to use shift instructions.
|
||||
@ -9750,9 +9735,9 @@ static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
|
||||
// X86 has dedicated unpack instructions that can handle specific blend
|
||||
// operations: UNPCKH and UNPCKL.
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 0, 8, 2, 10, 4, 12, 6, 14))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 1, 9, 3, 11, 5, 13, 7, 15))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
@ -9772,12 +9757,16 @@ static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
|
||||
// Use dedicated unpack instructions for masks that match their pattern.
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
0, 16, 1, 17, 4, 20, 5, 21,
|
||||
8, 24, 9, 25, 12, 28, 13, 29))
|
||||
{// First 128-bit lane.
|
||||
0, 16, 1, 17, 4, 20, 5, 21,
|
||||
// Second 128-bit lane.
|
||||
8, 24, 9, 25, 12, 28, 13, 29}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
2, 18, 3, 19, 6, 22, 7, 23,
|
||||
10, 26, 11, 27, 14, 30, 15, 31))
|
||||
{// First 128-bit lane.
|
||||
2, 18, 3, 19, 6, 22, 7, 23,
|
||||
// Second 128-bit lane.
|
||||
10, 26, 11, 27, 14, 30, 15, 31}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
@ -9797,9 +9786,9 @@ static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
|
||||
// X86 has dedicated unpack instructions that can handle specific blend
|
||||
// operations: UNPCKH and UNPCKL.
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 0, 8, 2, 10, 4, 12, 6, 14))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask, 1, 9, 3, 11, 5, 13, 7, 15))
|
||||
if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
@ -9819,12 +9808,16 @@ static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
||||
|
||||
// Use dedicated unpack instructions for masks that match their pattern.
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
0, 16, 1, 17, 4, 20, 5, 21,
|
||||
8, 24, 9, 25, 12, 28, 13, 29))
|
||||
{// First 128-bit lane.
|
||||
0, 16, 1, 17, 4, 20, 5, 21,
|
||||
// Second 128-bit lane.
|
||||
8, 24, 9, 25, 12, 28, 13, 29}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
2, 18, 3, 19, 6, 22, 7, 23,
|
||||
10, 26, 11, 27, 14, 30, 15, 31))
|
||||
{// First 128-bit lane.
|
||||
2, 18, 3, 19, 6, 22, 7, 23,
|
||||
// Second 128-bit lane.
|
||||
10, 26, 11, 27, 14, 30, 15, 31}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
@ -19881,9 +19874,9 @@ static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
|
||||
|
||||
// We're looking for blends between FADD and FSUB nodes. We insist on these
|
||||
// nodes being lined up in a specific expected pattern.
|
||||
if (!(isShuffleEquivalent(V1, V2, Mask, 0, 3) ||
|
||||
isShuffleEquivalent(V1, V2, Mask, 0, 5, 2, 7) ||
|
||||
isShuffleEquivalent(V1, V2, Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
|
||||
if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
|
||||
isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
|
||||
isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
|
||||
return SDValue();
|
||||
|
||||
// Only specific types are legal at this point, assert so we notice if and
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user