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There shalt be only one "immediate" operand type!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-04 17:21:20 +00:00
parent ceb408f6a2
commit 63b3d7113d
18 changed files with 51 additions and 86 deletions
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22
include/llvm/CodeGen/MachineInstr.h
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@ -62,8 +62,7 @@ public:
enum MachineOperandType { enum MachineOperandType {
MO_VirtualRegister, // virtual register for *value MO_VirtualRegister, // virtual register for *value
MO_SignExtendedImmed, MO_Immediate, // Immediate Operand
MO_UnextendedImmed,
MO_MachineBasicBlock, // MachineBasicBlock reference MO_MachineBasicBlock, // MachineBasicBlock reference
MO_FrameIndex, // Abstract Stack Frame Index MO_FrameIndex, // Abstract Stack Frame Index
MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
@ -160,9 +159,7 @@ public:
/// Accessors that tell you what kind of MachineOperand you're looking at. /// Accessors that tell you what kind of MachineOperand you're looking at.
/// ///
bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
bool isImmediate() const { bool isImmediate() const { return opType == MO_Immediate; }
return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
}
bool isFrameIndex() const { return opType == MO_FrameIndex; } bool isFrameIndex() const { return opType == MO_FrameIndex; }
bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; } bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
@ -380,7 +377,7 @@ public:
assert(!OperandsComplete() && assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
operands.push_back( operands.push_back(
MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); MachineOperand(intValue, MachineOperand::MO_Immediate));
} }
/// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument
@ -389,18 +386,7 @@ public:
void addZeroExtImm64Operand(uint64_t intValue) { void addZeroExtImm64Operand(uint64_t intValue) {
assert(!OperandsComplete() && assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
operands.push_back( operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate));
MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
}
/// addSignExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
void addSignExtImmOperand(int intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed));
} }
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {

7
include/llvm/CodeGen/MachineInstrBuilder.h
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@ -47,13 +47,6 @@ public:
return *this; return *this;
} }
/// addSImm - Add a new sign extended immediate operand...
///
const MachineInstrBuilder &addSImm(int val) const {
MI->addSignExtImmOperand(val);
return *this;
}
/// addZImm - Add a new zero extended immediate operand... /// addZImm - Add a new zero extended immediate operand...
/// ///
const MachineInstrBuilder &addZImm(unsigned Val) const { const MachineInstrBuilder &addZImm(unsigned Val) const {

10
lib/CodeGen/MachineInstr.cpp
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@ -160,10 +160,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_VirtualRegister:
OutputReg(OS, MO.getReg(), MRI); OutputReg(OS, MO.getReg(), MRI);
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
OS << (long)MO.getImmedValue();
break;
case MachineOperand::MO_UnextendedImmed:
OS << (long)MO.getImmedValue(); OS << (long)MO.getImmedValue();
break; break;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
@ -260,10 +257,7 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_VirtualRegister:
OutputReg(OS, MO.getReg()); OutputReg(OS, MO.getReg());
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
OS << (long)MO.getImmedValue();
break;
case MachineOperand::MO_UnextendedImmed:
OS << (long)MO.getImmedValue(); OS << (long)MO.getImmedValue();
break; break;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:

3
lib/Target/Alpha/AlphaAsmPrinter.cpp
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@ -97,8 +97,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
O << RI.get(MO.getReg()).Name; O << RI.get(MO.getReg()).Name;
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed:
std::cerr << "printOp() does not handle immediate values\n"; std::cerr << "printOp() does not handle immediate values\n";
abort(); abort();
return; return;

4
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@ -234,14 +234,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
//inst off the SP/FP //inst off the SP/FP
//fix up the old: //fix up the old:
MI.SetMachineOperandReg(i + 1, Alpha::R28); MI.SetMachineOperandReg(i + 1, Alpha::R28);
MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
getLower16(Offset)); getLower16(Offset));
//insert the new //insert the new
MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
MBB.insert(II, nMI); MBB.insert(II, nMI);
} else { } else {
MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
} }
} }

7
lib/Target/IA64/IA64AsmPrinter.cpp
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@ -170,16 +170,15 @@ bool IA64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
} }
void IA64AsmPrinter::printOp(const MachineOperand &MO, void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool isBRCALLinsn /* = false */) { bool isBRCALLinsn /* = false */) {
const MRegisterInfo &RI = *TM.getRegisterInfo(); const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_VirtualRegister:
O << RI.get(MO.getReg()).Name; O << RI.get(MO.getReg()).Name;
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed: O << MO.getImmedValue();
O << /*(unsigned int)*/MO.getImmedValue();
return; return;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock()); printBasicBlockLabel(MO.getMachineBasicBlock());

6
lib/Target/IA64/IA64InstrBuilder.h
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@ -29,9 +29,9 @@ inline const MachineInstrBuilder&
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
bool mem = true) { bool mem = true) {
if (mem) if (mem)
return MIB.addSImm(Offset).addFrameIndex(FI); return MIB.addImm(Offset).addFrameIndex(FI);
else else
return MIB.addFrameIndex(FI).addSImm(Offset); return MIB.addFrameIndex(FI).addImm(Offset);
} }
/// addConstantPoolReference - This function is used to add a reference to the /// addConstantPoolReference - This function is used to add a reference to the
@ -43,7 +43,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
inline const MachineInstrBuilder& inline const MachineInstrBuilder&
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
int Offset = 0) { int Offset = 0) {
return MIB.addSImm(Offset).addConstantPoolIndex(CPI); return MIB.addImm(Offset).addConstantPoolIndex(CPI);
} }
} // End llvm namespace } // End llvm namespace

10
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -122,11 +122,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New; MachineInstr *New;
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(-Amount); .addImm(-Amount);
} else { } else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
.addSImm(Amount); .addImm(Amount);
} }
// Replace the pseudo instruction with a new instruction... // Replace the pseudo instruction with a new instruction...
@ -173,7 +173,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// (the bundler wants to know this) // (the bundler wants to know this)
//insert the new //insert the new
MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
.addReg(BaseRegister).addSImm(Offset); .addReg(BaseRegister).addImm(Offset);
MBB.insert(II, nMI); MBB.insert(II, nMI);
} else { // it's big } else { // it's big
//fix up the old: //fix up the old:
@ -181,7 +181,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
MI.getOperand(i).setUse(); // mark r22 as being used MI.getOperand(i).setUse(); // mark r22 as being used
// (the bundler wants to know this) // (the bundler wants to know this)
MachineInstr* nMI; MachineInstr* nMI;
nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset); nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
MBB.insert(II, nMI); MBB.insert(II, nMI);
nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister) nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22); .addReg(IA64::r22);
@ -272,7 +272,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes); MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
MBB.insert(MBBI, MI); MBB.insert(MBBI, MI);
} else { // we use r22 as a scratch register here } else { // we use r22 as a scratch register here
MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes); MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm // FIXME: MOVLSI32 expects a _u_32imm
MBB.insert(MBBI, MI); // first load the decrement into r22 MBB.insert(MBBI, MI); // first load the decrement into r22
MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);

3
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -356,8 +356,7 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
O << RI.get(MO.getReg()).Name; O << RI.get(MO.getReg()).Name;
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed:
std::cerr << "printOp() does not handle immediate values\n"; std::cerr << "printOp() does not handle immediate values\n";
abort(); abort();
return; return;

2
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -131,7 +131,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
if (Displacement >= -32768 && Displacement <= 32767) { if (Displacement >= -32768 && Displacement <= 32767) {
BuildMI(*MBB, MBBJ, Opcode, 2).addReg(CRReg).addMBB(trueMBB); BuildMI(*MBB, MBBJ, Opcode, 2).addReg(CRReg).addMBB(trueMBB);
} else { } else {
BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8); BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addImm(8);
BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB); BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB);
} }

6
lib/Target/PowerPC/PPCInstrBuilder.h
View File

@ -33,9 +33,9 @@ inline const MachineInstrBuilder&
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
bool mem = true) { bool mem = true) {
if (mem) if (mem)
return MIB.addSImm(Offset).addFrameIndex(FI); return MIB.addImm(Offset).addFrameIndex(FI);
else else
return MIB.addFrameIndex(FI).addSImm(Offset); return MIB.addFrameIndex(FI).addImm(Offset);
} }
/// addConstantPoolReference - This function is used to add a reference to the /// addConstantPoolReference - This function is used to add a reference to the
@ -47,7 +47,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
inline const MachineInstrBuilder& inline const MachineInstrBuilder&
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
int Offset = 0) { int Offset = 0) {
return MIB.addSImm(Offset).addConstantPoolIndex(CPI); return MIB.addImm(Offset).addConstantPoolIndex(CPI);
} }
} // End llvm namespace } // End llvm namespace

25
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -269,10 +269,10 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// Replace the pseudo instruction with a new instruction... // Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
} else { } else {
assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
} }
} }
} }
@ -311,7 +311,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (Offset > 32767 || Offset < -32768) { if (Offset > 32767 || Offset < -32768) {
// Insert a set of r0 with the full offset value before the ld, st, or add // Insert a set of r0 with the full offset value before the ld, st, or add
MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock *MBB = MI.getParent();
BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
// convert into indexed form of the instruction // convert into indexed form of the instruction
@ -333,8 +333,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
Offset >>= 2; // The actual encoded value has the low two bits zero. Offset >>= 2; // The actual encoded value has the low two bits zero.
break; break;
} }
MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
Offset);
} }
} }
@ -511,14 +510,14 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
.addSImm(MaxAlign-NumBytes); .addImm(MaxAlign-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3) BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes <= 32768) { } else if (NumBytes <= 32768) {
BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes) BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
.addReg(PPC::R1); .addReg(PPC::R1);
} else { } else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
.addImm(NegNumbytes & 0xFFFF); .addImm(NegNumbytes & 0xFFFF);
BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
@ -534,13 +533,13 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
Moves.push_back(new MachineMove(LabelID, Dst, Src)); Moves.push_back(new MachineMove(LabelID, Dst, Src));
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
} }
// If there is a frame pointer, copy R1 (SP) into R31 (FP) // If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (HasFP) { if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3) BuildMI(MBB, MBBI, PPC::STW, 3)
.addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
} }
} }
@ -564,16 +563,16 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
// its stack slot. // its stack slot.
if (hasFP(MF)) { if (hasFP(MF)) {
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
.addSImm(GPRSize).addReg(PPC::R31); .addImm(GPRSize).addReg(PPC::R31);
} }
// The loaded (or persistent) stack pointer value is offseted by the 'stwu' // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
// on entry to the function. Add this offset back now. // on entry to the function. Add this offset back now.
if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
.addReg(PPC::R1).addSImm(NumBytes); .addReg(PPC::R1).addImm(NumBytes);
} else { } else {
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
} }
} }
} }

6
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -153,8 +153,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
O << "%reg" << MO.getReg(); O << "%reg" << MO.getReg();
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed:
O << (int)MO.getImmedValue(); O << (int)MO.getImmedValue();
break; break;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
@ -192,8 +191,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
if (OpTy == MachineOperand::MO_VirtualRegister && if (OpTy == MachineOperand::MO_VirtualRegister &&
MI->getOperand(opNum+1).getReg() == SP::G0) MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0" return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed || if (OpTy == MachineOperand::MO_Immediate &&
OpTy == MachineOperand::MO_UnextendedImmed) &&
MI->getOperand(opNum+1).getImmedValue() == 0) MI->getOperand(opNum+1).getImmedValue() == 0)
return; // don't print "+0" return; // don't print "+0"

6
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -111,7 +111,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size; Size = -Size;
if (Size) if (Size)
BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size); BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I); MBB.erase(I);
} }
@ -136,7 +136,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
// If the offset is small enough to fit in the immediate field, directly // If the offset is small enough to fit in the immediate field, directly
// encode it. // encode it.
MI.SetMachineOperandReg(i, SP::I6); MI.SetMachineOperandReg(i, SP::I6);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset); MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
} else { } else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time. // scavenge a register here instead of reserving G1 all of the time.
@ -147,7 +147,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
SP::G1).addReg(SP::G1).addReg(SP::I6); SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user. // Insert: G1+%lo(offset) into the user.
MI.SetMachineOperandReg(i, SP::G1); MI.SetMachineOperandReg(i, SP::G1);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed, MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
Offset & ((1 << 10)-1)); Offset & ((1 << 10)-1));
} }
} }

3
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -116,8 +116,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
O << (char)tolower(*Name); O << (char)tolower(*Name);
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed:
if (!Modifier || strcmp(Modifier, "debug") != 0) if (!Modifier || strcmp(Modifier, "debug") != 0)
O << '$'; O << '$';
O << (int)MO.getImmedValue(); O << (int)MO.getImmedValue();

12
lib/Target/X86/X86InstrBuilder.h
View File

@ -61,7 +61,7 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
unsigned Reg) { unsigned Reg) {
// Because memory references are always represented with four // Because memory references are always represented with four
// values, this adds: Reg, [1, NoReg, 0] to the instruction. // values, this adds: Reg, [1, NoReg, 0] to the instruction.
return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(0); return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0);
} }
@ -71,14 +71,14 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
/// ///
inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
unsigned Reg, int Offset) { unsigned Reg, int Offset) {
return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(Offset); return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset);
} }
/// addRegReg - This function is used to add a memory reference of the form: /// addRegReg - This function is used to add a memory reference of the form:
/// [Reg + Reg]. /// [Reg + Reg].
inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
unsigned Reg1, unsigned Reg2) { unsigned Reg1, unsigned Reg2) {
return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addSImm(0); return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0);
} }
inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
@ -95,7 +95,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
if (AM.GV) if (AM.GV)
return MIB.addGlobalAddress(AM.GV, AM.Disp); return MIB.addGlobalAddress(AM.GV, AM.Disp);
else else
return MIB.addSImm(AM.Disp); return MIB.addImm(AM.Disp);
} }
/// addFrameReference - This function is used to add a reference to the base of /// addFrameReference - This function is used to add a reference to the base of
@ -105,7 +105,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
/// ///
inline const MachineInstrBuilder & inline const MachineInstrBuilder &
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addSImm(Offset); return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset);
} }
/// addConstantPoolReference - This function is used to add a reference to the /// addConstantPoolReference - This function is used to add a reference to the
@ -117,7 +117,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
inline const MachineInstrBuilder & inline const MachineInstrBuilder &
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
int Offset = 0) { int Offset = 0) {
return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset); return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset);
} }
} // End llvm namespace } // End llvm namespace

3
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -107,8 +107,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
O << "reg" << MO.getReg(); O << "reg" << MO.getReg();
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_Immediate:
case MachineOperand::MO_UnextendedImmed:
O << (int)MO.getImmedValue(); O << (int)MO.getImmedValue();
return; return;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:

2
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -676,7 +676,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
else else
Offset += 4; // Skip the saved EBP Offset += 4; // Skip the saved EBP
MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset); MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
} }
void void