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[AVX512] Added lowering for VBROADCASTSS/SD instructions.
Lowering patterns were written through avx512_broadcast_pat multiclass as pattern generates VBROADCAST and COPY_TO_REGCLASS nodes. Added lowering tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223804 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
dad20b2ae2
commit
648f7c7eb1
@ -651,6 +651,44 @@ let ExeDomain = SSEPackedDouble in {
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avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
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}
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// SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
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// representations of source
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multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
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X86VectorVTInfo _, RegisterClass SrcRC_v,
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RegisterClass SrcRC_s> {
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def : Pat<(_.VT (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src))),
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(!cast<Instruction>(InstName##"r")
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(COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
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let AddedComplexity = 30 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),
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_.RC:$src0)),
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(!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
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(COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
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def : Pat<(_.VT(vselect _.KRCWM:$mask,
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(OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),
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_.ImmAllZerosV)),
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(!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
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(COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
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}
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}
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defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
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VR128X, FR32X>;
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defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
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VR128X, FR64X>;
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let Predicates = [HasVLX] in {
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defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
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v8f32x_info, VR128X, FR32X>;
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defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
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v4f32x_info, VR128X, FR32X>;
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defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
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v4f64x_info, VR128X, FR64X>;
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}
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def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
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(VBROADCASTSSZm addr:$src)>;
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def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
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@ -659,6 +659,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
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{ X86::VPABSDZrr, X86::VPABSDZrm, 0 },
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{ X86::VPABSQZrr, X86::VPABSQZrm, 0 },
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{ X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
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// AVX-512 foldable instructions (256-bit versions)
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{ X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
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{ X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
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@ -670,6 +672,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
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{ X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
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{ X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
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{ X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
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// AVX-512 foldable instructions (256-bit versions)
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{ X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
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{ X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
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@ -681,6 +685,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
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{ X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
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{ X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
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{ X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
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// AES foldable instructions
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{ X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
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@ -1321,6 +1326,13 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
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{ X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
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{ X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
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{ X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
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// AVX-512{F,VL} foldable instructions
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{ X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
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{ X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
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// AES foldable instructions
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{ X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
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@ -1501,7 +1513,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
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{ X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
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{ X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
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{ X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
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{ X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
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{ X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
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{ X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
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{ X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
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{ X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
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@ -20,6 +20,14 @@ define <8 x i64> @_inreg8xi64(i64 %a) {
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ret <8 x i64> %c
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}
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;CHECK-LABEL: _ss16xfloat_v4
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;CHECK: vbroadcastss %xmm0, %zmm0
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;CHECK: ret
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define <16 x float> @_ss16xfloat_v4(<4 x float> %a) {
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%b = shufflevector <4 x float> %a, <4 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %b
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}
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define <16 x float> @_inreg16xfloat(float %a) {
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; CHECK-LABEL: _inreg16xfloat:
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; CHECK: ## BB#0:
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@ -30,6 +38,62 @@ define <16 x float> @_inreg16xfloat(float %a) {
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ret <16 x float> %c
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}
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;CHECK-LABEL: _ss16xfloat_mask:
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;CHECK: vbroadcastss %xmm0, %zmm1 {%k1}
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;CHECK: ret
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define <16 x float> @_ss16xfloat_mask(float %a, <16 x float> %i, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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%r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i
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ret <16 x float> %r
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}
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;CHECK-LABEL: _ss16xfloat_maskz:
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;CHECK: vbroadcastss %xmm0, %zmm0 {%k1} {z}
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;CHECK: ret
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define <16 x float> @_ss16xfloat_maskz(float %a, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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%r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer
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ret <16 x float> %r
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}
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;CHECK-LABEL: _ss16xfloat_load:
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;CHECK: vbroadcastss (%{{.*}}, %zmm
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;CHECK: ret
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define <16 x float> @_ss16xfloat_load(float* %a.ptr) {
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%a = load float* %a.ptr
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %c
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}
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;CHECK-LABEL: _ss16xfloat_mask_load:
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;CHECK: vbroadcastss (%rdi), %zmm0 {%k1}
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;CHECK: ret
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define <16 x float> @_ss16xfloat_mask_load(float* %a.ptr, <16 x float> %i, <16 x i32> %mask1) {
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%a = load float* %a.ptr
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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%r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i
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ret <16 x float> %r
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}
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;CHECK-LABEL: _ss16xfloat_maskz_load:
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;CHECK: vbroadcastss (%rdi), %zmm0 {%k1} {z}
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;CHECK: ret
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define <16 x float> @_ss16xfloat_maskz_load(float* %a.ptr, <16 x i32> %mask1) {
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%a = load float* %a.ptr
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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%r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer
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ret <16 x float> %r
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}
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define <8 x double> @_inreg8xdouble(double %a) {
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; CHECK-LABEL: _inreg8xdouble:
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; CHECK: ## BB#0:
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@ -40,6 +104,62 @@ define <8 x double> @_inreg8xdouble(double %a) {
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ret <8 x double> %c
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}
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;CHECK-LABEL: _sd8xdouble_mask:
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;CHECK: vbroadcastsd %xmm0, %zmm1 {%k1}
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;CHECK: ret
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define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i
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ret <8 x double> %r
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}
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;CHECK-LABEL: _sd8xdouble_maskz:
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;CHECK: vbroadcastsd %xmm0, %zmm0 {%k1} {z}
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;CHECK: ret
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define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer
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ret <8 x double> %r
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}
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;CHECK-LABEL: _sd8xdouble_load:
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;CHECK: vbroadcastsd (%rdi), %zmm
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;CHECK: ret
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define <8 x double> @_sd8xdouble_load(double* %a.ptr) {
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%a = load double* %a.ptr
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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ret <8 x double> %c
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}
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;CHECK-LABEL: _sd8xdouble_mask_load:
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;CHECK: vbroadcastsd (%rdi), %zmm0 {%k1}
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;CHECK: ret
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define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {
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%a = load double* %a.ptr
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i
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ret <8 x double> %r
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}
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define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) {
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; CHECK-LABEL: _sd8xdouble_maskz_load:
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; CHECK: vbroadcastsd (%rdi), %zmm0 {%k1} {z}
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; CHECK: ret
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%a = load double* %a.ptr
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%mask = icmp ne <8 x i32> %mask1, zeroinitializer
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer
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ret <8 x double> %r
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}
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define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
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; CHECK-LABEL: _xmm16xi32:
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; CHECK: ## BB#0:
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