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VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
50d280c14e
commit
6557bce3ec
@ -155,10 +155,11 @@ namespace ARMII {
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//===------------------------------------------------------------------===//
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// Code domain.
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DomainShift = 18,
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DomainMask = 3 << DomainShift,
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DomainMask = 7 << DomainShift,
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DomainGeneral = 0 << DomainShift,
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DomainVFP = 1 << DomainShift,
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DomainNEON = 2 << DomainShift,
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DomainNEONA8 = 4 << DomainShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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@ -21,17 +21,14 @@ static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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// FIXME: Detect integer instructions properly.
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Domain = TID.TSFlags & ARMII::DomainMask;
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if (Domain == ARMII::DomainVFP) {
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD ||
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Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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} else if (Domain == ARMII::DomainNEON) {
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if (MI->getDesc().mayStore() || MI->getDesc().mayLoad())
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return false;
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} else
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if (TID.mayStore())
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return false;
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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unsigned Opcode = TID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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return false;
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}
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ScheduleHazardRecognizer::HazardType
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@ -127,13 +127,14 @@ def IndexModePost : IndexMode<2>;
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def IndexModeUpd : IndexMode<3>;
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// Instruction execution domain.
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class Domain<bits<2> val> {
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bits<2> Value = val;
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class Domain<bits<3> val> {
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bits<3> Value = val;
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}
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def GenericDomain : Domain<0>;
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def VFPDomain : Domain<1>; // Instructions in VFP domain only
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def NeonDomain : Domain<2>; // Instructions in Neon domain only
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def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
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def VFPNeonA8Domain : Domain<7>; // Instructions in VFP & Neon under A8
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//===----------------------------------------------------------------------===//
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// ARM special operands.
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@ -249,7 +250,7 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
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let TSFlags{15-10} = Form;
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let TSFlags{16} = isUnaryDataProc;
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let TSFlags{17} = canXformTo16Bit;
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let TSFlags{19-18} = D.Value;
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let TSFlags{20-18} = D.Value;
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let Constraints = cstr;
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let Itinerary = itin;
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@ -197,9 +197,9 @@ def VADDS : ASbIn<0b11100, 0b11, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VSUBD : ADbI<0b11100, 0b11, 1, 0,
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@ -211,9 +211,9 @@ def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VDIVD : ADbI<0b11101, 0b00, 0, 0,
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@ -235,9 +235,9 @@ def VMULS : ASbIn<0b11100, 0b10, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VNMULD : ADbI<0b11100, 0b10, 1, 0,
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@ -249,9 +249,9 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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// Match reassociated forms only if not sign dependent rounding.
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@ -271,9 +271,9 @@ def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
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(outs), (ins SPR:$Sd, SPR:$Sm),
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IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
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[(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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// FIXME: Verify encoding after integrated assembler is working.
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@ -286,9 +286,9 @@ def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
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(outs), (ins SPR:$Sd, SPR:$Sm),
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IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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} // Defs = [FPSCR]
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@ -305,9 +305,9 @@ def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
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[(set SPR:$Sd, (fabs SPR:$Sm))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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let Defs = [FPSCR] in {
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@ -326,9 +326,9 @@ def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
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let Inst{3-0} = 0b0000;
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let Inst{5} = 0;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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// FIXME: Verify encoding after integrated assembler is working.
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@ -347,9 +347,9 @@ def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
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let Inst{3-0} = 0b0000;
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let Inst{5} = 0;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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} // Defs = [FPSCR]
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@ -423,9 +423,9 @@ def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
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[(set SPR:$Sd, (fneg SPR:$Sm))]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
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@ -598,9 +598,9 @@ def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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[(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
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let Inst{7} = 1; // s32
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
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@ -616,9 +616,9 @@ def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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[(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
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let Inst{7} = 0; // u32
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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// FP -> Int:
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@ -671,9 +671,9 @@ def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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[(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
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let Inst{7} = 1; // Z bit
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
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@ -689,9 +689,9 @@ def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
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[(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
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let Inst{7} = 1; // Z bit
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
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@ -743,36 +743,36 @@ def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
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@ -801,36 +801,36 @@ def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
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(outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
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IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
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@ -874,9 +874,9 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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@ -901,9 +901,9 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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}
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def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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@ -928,9 +928,9 @@ def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
|
||||
Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and VFP
|
||||
// pipelines.
|
||||
let D = VFPNeonDomain;
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines on A8.
|
||||
let D = VFPNeonA8Domain;
|
||||
}
|
||||
|
||||
def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
|
||||
@ -954,9 +954,9 @@ def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
|
||||
[(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
|
||||
RegConstraint<"$Sdin = $Sd">,
|
||||
Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and VFP
|
||||
// pipelines.
|
||||
let D = VFPNeonDomain;
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines on A8.
|
||||
let D = VFPNeonA8Domain;
|
||||
}
|
||||
|
||||
def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
|
||||
@ -995,9 +995,9 @@ def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
|
||||
IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
|
||||
[/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
|
||||
RegConstraint<"$Sn = $Sd"> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and VFP
|
||||
// pipelines.
|
||||
let D = VFPNeonDomain;
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines on A8.
|
||||
let D = VFPNeonA8Domain;
|
||||
}
|
||||
} // neverHasSideEffects
|
||||
|
||||
|
||||
@ -132,22 +132,16 @@ unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
|
||||
}
|
||||
|
||||
bool MLxExpansion::hasRAWHazard(unsigned Reg, MachineInstr *MI) const {
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
// FIXME: Detect integer instructions properly.
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
unsigned Domain = TID.TSFlags & ARMII::DomainMask;
|
||||
if (Domain == ARMII::DomainVFP) {
|
||||
unsigned Opcode = TID.getOpcode();
|
||||
if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD ||
|
||||
Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
||||
return false;
|
||||
} else if (Domain == ARMII::DomainNEON) {
|
||||
if (TID.mayStore() || TID.mayLoad())
|
||||
return false;
|
||||
} else {
|
||||
if (TID.mayStore())
|
||||
return false;
|
||||
}
|
||||
|
||||
return MI->readsRegister(Reg, TRI);
|
||||
unsigned Opcode = TID.getOpcode();
|
||||
if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
||||
return false;
|
||||
if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
|
||||
return MI->readsRegister(Reg, TRI);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
@ -35,6 +35,7 @@ namespace {
|
||||
private:
|
||||
const TargetRegisterInfo *TRI;
|
||||
const ARMBaseInstrInfo *TII;
|
||||
bool isA8;
|
||||
|
||||
typedef DenseMap<unsigned, const MachineInstr*> RegMap;
|
||||
|
||||
@ -43,6 +44,16 @@ namespace {
|
||||
char NEONMoveFixPass::ID = 0;
|
||||
}
|
||||
|
||||
static bool inNEONDomain(unsigned Domain, bool isA8) {
|
||||
if (Domain & ARMII::DomainNEON) {
|
||||
// Some instructions only go down NEON pipeline when executed on CortexA8.
|
||||
if (Domain & ARMII::DomainNEONA8)
|
||||
return isA8;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
|
||||
RegMap Defs;
|
||||
bool Modified = false;
|
||||
@ -70,7 +81,7 @@ bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
|
||||
Domain = ARMII::DomainNEON;
|
||||
}
|
||||
|
||||
if (Domain & ARMII::DomainNEON) {
|
||||
if (inNEONDomain(Domain, isA8)) {
|
||||
// Convert VMOVD to VMOVDneon
|
||||
unsigned DestReg = MI->getOperand(0).getReg();
|
||||
|
||||
@ -123,6 +134,7 @@ bool NEONMoveFixPass::runOnMachineFunction(MachineFunction &Fn) {
|
||||
|
||||
TRI = TM.getRegisterInfo();
|
||||
TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
|
||||
isA8 = TM.getSubtarget<ARMSubtarget>().isCortexA8();
|
||||
|
||||
bool Modified = false;
|
||||
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user