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LLVM incorrectly folds xor into select

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LLVM replaces the SelectionDAG pattern (xor (set_cc cc x y) 1) with
(set_cc !cc x y), which is only correct when the xor has type i1.
Instead, we should check that the constant operand to the xor is all
ones.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard 2014-11-11 17:36:01 +00:00
parent 328bc2f89e
commit 659b1491b8
2 changed files with 19 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3826,7 +3826,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
return RXOR;
// fold !(x cc y) -> (x !cc y)
if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
if (N1C && N1C->getAPIntValue().isAllOnesValue() &&
isSetCCEquivalent(N0, LHS, RHS, CC)) {
bool isInt = LHS.getValueType().isInteger();
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
isInt);

17
test/CodeGen/ARM/select_xform.ll
View File

@ -222,3 +222,20 @@ entry:
%add = add i32 %conv, %c
ret i32 %add
}
; Do not fold the xor into the select
define i32 @t15(i32 %p1, i32 %p2, i32 %p3) {
entry:
; ARM: cmp r0, #8
; ARM: mov{{(le|gt)}} [[REG:r[0-9]+]], {{r[0-9]+}}
; ARM: eor r0, [[REG]], #1
; T2: cmp r0, #8
; T2: it [[CC:(le|gt)]]
; T2: mov[[CC]] [[REG:r[0-9]+]], {{r[0-9]+}}
; T2: eor r0, [[REG:r[0-9]+]], #1
%cmp = icmp sgt i32 %p1, 8
%a = select i1 %cmp, i32 %p2, i32 %p3
%xor = xor i32 %a, 1
ret i32 %xor
}