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[WebAssembly] Annotate call and load/store immediates.

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These will be used to guide the binary encoding of these immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290412 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2016-12-23 03:23:52 +00:00
parent e365f8338a
commit 66b35bd23b
4 changed files with 36 additions and 26 deletions
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4
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
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@ -55,6 +55,10 @@ enum OperandType {
OPERAND_F32IMM,
/// 64-bit floating-point immediates.
OPERAND_F64IMM,
/// 32-bit unsigned function indices.
OPERAND_FUNCTION32,
/// 32-bit unsigned memory offsets.
OPERAND_OFFSET32,
/// p2align immediate for load and store address alignment.
OPERAND_P2ALIGN,
/// signature immediate for block/loop.

6
lib/Target/WebAssembly/WebAssemblyInstrCall.td
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@ -26,7 +26,7 @@ def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
} // isCodeGenOnly = 1
multiclass CALL<WebAssemblyRegClass vt, string prefix> {
def CALL_#vt : I<(outs vt:$dst), (ins i32imm:$callee, variable_ops),
def CALL_#vt : I<(outs vt:$dst), (ins function32_op:$callee, variable_ops),
[(set vt:$dst, (WebAssemblycall1 (i32 imm:$callee)))],
!strconcat(prefix, "call\t$dst, $callee"),
0x10>;
@ -43,7 +43,7 @@ multiclass CALL<WebAssemblyRegClass vt, string prefix> {
}
multiclass SIMD_CALL<ValueType vt, string prefix> {
def CALL_#vt : SIMD_I<(outs V128:$dst), (ins i32imm:$callee, variable_ops),
def CALL_#vt : SIMD_I<(outs V128:$dst), (ins function32_op:$callee, variable_ops),
[(set (vt V128:$dst),
(WebAssemblycall1 (i32 imm:$callee)))],
!strconcat(prefix, "call\t$dst, $callee"),
@ -73,7 +73,7 @@ let Uses = [SP32, SP64], isCall = 1 in {
defm : SIMD_CALL<v4i32, "i32x4.">;
defm : SIMD_CALL<v4f32, "f32x4.">;
def CALL_VOID : I<(outs), (ins i32imm:$callee, variable_ops),
def CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
[(WebAssemblycall0 (i32 imm:$callee))],
"call \t$callee", 0x10>;
let isCodeGenOnly = 1 in {

6
lib/Target/WebAssembly/WebAssemblyInstrInfo.td
View File

@ -86,6 +86,12 @@ def f32imm_op : Operand<f32>;
let OperandType = "OPERAND_F64IMM" in
def f64imm_op : Operand<f64>;
let OperandType = "OPERAND_FUNCTION32" in
def function32_op : Operand<i32>;
let OperandType = "OPERAND_OFFSET32" in
def offset32_op : Operand<i32>;
let OperandType = "OPERAND_P2ALIGN" in {
def P2Align : Operand<i32> {
let PrintMethod = "printWebAssemblyP2AlignOperand";

46
lib/Target/WebAssembly/WebAssemblyInstrMemory.td
View File

@ -59,16 +59,16 @@ let Defs = [ARGUMENTS] in {
// FIXME: When we can break syntax compatibility, reorder the fields in the
// asmstrings to match the binary encoding.
def LOAD_I32 : I<(outs I32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i32.load\t$dst, ${off}(${addr})${p2align}", 0x28>;
def LOAD_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load\t$dst, ${off}(${addr})${p2align}", 0x29>;
def LOAD_F32 : I<(outs F32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "f32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>;
def LOAD_F64 : I<(outs F64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "f64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>;
} // Defs = [ARGUMENTS]
@ -143,34 +143,34 @@ let Defs = [ARGUMENTS] in {
// Extending load.
def LOAD8_S_I32 : I<(outs I32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x2c>;
def LOAD8_U_I32 : I<(outs I32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x2d>;
def LOAD16_S_I32 : I<(outs I32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x2e>;
def LOAD16_U_I32 : I<(outs I32:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x2f>;
def LOAD8_S_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x30>;
def LOAD8_U_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x31>;
def LOAD16_S_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x32>;
def LOAD16_U_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x33>;
def LOAD32_S_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x34>;
def LOAD32_U_I64 : I<(outs I64:$dst),
(ins P2Align:$p2align, i32imm:$off, I32:$addr),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[], "i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x35>;
} // Defs = [ARGUMENTS]
@ -449,16 +449,16 @@ let Defs = [ARGUMENTS] in {
// Basic store.
// Note: WebAssembly inverts SelectionDAG's usual operand order.
def STORE_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I32:$val), [],
"i32.store\t${off}(${addr})${p2align}, $val", 0x36>;
def STORE_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I64:$val), [],
"i64.store\t${off}(${addr})${p2align}, $val", 0x37>;
def STORE_F32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE_F32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
F32:$val), [],
"f32.store\t${off}(${addr})${p2align}, $val", 0x38>;
def STORE_F64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE_F64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
F64:$val), [],
"f64.store\t${off}(${addr})${p2align}, $val", 0x39>;
@ -541,19 +541,19 @@ def : Pat<(store F64:$val, (WebAssemblywrapper texternalsym:$off)),
let Defs = [ARGUMENTS] in {
// Truncating store.
def STORE8_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE8_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I32:$val), [],
"i32.store8\t${off}(${addr})${p2align}, $val", 0x3a>;
def STORE16_I32 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE16_I32 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I32:$val), [],
"i32.store16\t${off}(${addr})${p2align}, $val", 0x3b>;
def STORE8_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE8_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I64:$val), [],
"i64.store8\t${off}(${addr})${p2align}, $val", 0x3c>;
def STORE16_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE16_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I64:$val), [],
"i64.store16\t${off}(${addr})${p2align}, $val", 0x3d>;
def STORE32_I64 : I<(outs), (ins P2Align:$p2align, i32imm:$off, I32:$addr,
def STORE32_I64 : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr,
I64:$val), [],
"i64.store32\t${off}(${addr})${p2align}, $val", 0x3e>;