[PowerPC/MIR Serialization] Target flags serialization support

Add support for MIR serialization of PowerPC-specific operand target flags (based on the generic infrastructure added in r244185 and r245383). I won't even pretend that this is good test coverage, but this includes the regression test associated with r246372. Adding an MIR test for that fix is far superior to adding an IR-level test because particular instruction-scheduling decisions are necessary in order to expose the bug, and using an MIR test we can start the pipeline post-scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246373 91177308-0d34-0410-b5e6-96231b3b80d8
2024-11-24 12:19:53 +00:00 · 2015-08-30 07:50:35 +00:00 · 2015-08-30 07:50:35 +00:00 · 673129f5d5
commit 673129f5d5
parent 0977a23c2a
3 changed files with 121 additions and 0 deletions
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@ -1992,3 +1992,35 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
  }
 }

+std::pair<unsigned, unsigned>
+PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
+  const unsigned Mask = PPCII::MO_ACCESS_MASK;
+  return std::make_pair(TF & Mask, TF & ~Mask);
+}
+
+ArrayRef<std::pair<unsigned, const char *>>
+PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
+  using namespace PPCII;
+  static std::pair<unsigned, const char *> TargetFlags[] = {
+      {MO_LO, "ppc-lo"},
+      {MO_HA, "ppc-ha"},
+      {MO_TPREL_LO, "ppc-tprel-lo"},
+      {MO_TPREL_HA, "ppc-tprel-ha"},
+      {MO_DTPREL_LO, "ppc-dtprel-lo"},
+      {MO_TLSLD_LO, "ppc-tlsld-lo"},
+      {MO_TOC_LO, "ppc-toc-lo"},
+      {MO_TLS, "ppc-tls"}};
+  return makeArrayRef(TargetFlags);
+}
+
+ArrayRef<std::pair<unsigned, const char *>>
+PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
+  using namespace PPCII;
+  static std::pair<unsigned, const char *> TargetFlags[] = {
+      {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
+      {MO_PIC_FLAG, "ppc-pic"},
+      {MO_NLP_FLAG, "ppc-nlp"},
+      {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
+  return makeArrayRef(TargetFlags);
+}
+
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@ -271,6 +271,15 @@ public:
  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;

  void getNoopForMachoTarget(MCInst &NopInst) const override;
+
+  std::pair<unsigned, unsigned>
+  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
+
+  ArrayRef<std::pair<unsigned, const char *>>
+  getSerializableDirectMachineOperandTargetFlags() const override;
+
+  ArrayRef<std::pair<unsigned, const char *>>
+  getSerializableBitmaskMachineOperandTargetFlags() const override;
 };

 }
--- a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@ -0,0 +1,80 @@
+# RUN: llc -relocation-model=pic -start-after=block-placement -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  
+  @x = internal thread_local unnamed_addr global i1 false
+  @y = external thread_local global i32, align 4
+  
+  ; Function Attrs: nounwind
+  define void @test1() #0 {
+  entry:
+    store i1 true, i1* @x, align 1
+    store i32 20, i32* @y, align 4
+    ret void
+  }
+  
+  attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="pwr7" }
+  
+  !llvm.module.flags = !{!0}
+  
+  !0 = !{i32 1, !"PIC Level", i32 2}
+
+...
+---
+name:            test1
+alignment:       4
+exposesReturnsTwice: false
+hasInlineAsm:    false
+isSSA:           false
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       64
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 48
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+fixedStack:      
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
+  - { id: 1, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
+body:             |
+  bb.0.entry:
+    liveins: %x30, %x30
+  
+    %x0 = MFLR8 implicit %lr8
+    STD %x31, -8, %x1
+    STD killed %x0, 16, %x1
+    %x1 = STDU %x1, -64, %x1
+    %x3 = ADDIStlsldHA %x2, @x
+    %x31 = OR8 %x1, %x1
+    %x3 = ADDItlsldL killed %x3, @x
+    STD killed %x30, 48, %x31 :: (store 8 into %fixed-stack.0, align 16)
+    %x3 = GETtlsldADDR killed %x3, @x, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
+    %x12 = ADDIStlsgdHA %x2, @y
+    %x30 = OR8 killed %x3, %x3
+    %x3 = ADDItlsgdL killed %x12, @y
+    %x3 = GETtlsADDR killed %x3, @y, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
+    %x4 = ADDISdtprelHA killed %x30, @x
+    ; CHECK: addis 4, 30, x@dtprel@ha
+    %x5 = LI8 1
+    %r6 = LI 20
+    %x30 = LD 48, %x31 :: (load 8 from %fixed-stack.0, align 16)
+    STB8 killed %x5, target-flags(ppc-dtprel-lo) @x, killed %x4 :: (store 1 into @x)
+    STW killed %r6, 0, killed %x3 :: (store 4 into @y)
+    %x1 = ADDI8 %x1, 64
+    %x0 = LD 16, %x1
+    %x31 = LD -8, %x1
+    MTLR8 killed %x0, implicit-def %lr8
+    BLR8 implicit %lr8, implicit %rm
+
+...