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Put int the getReg cast optimization from x86 so that we generate fewer

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move instructions for the register allocator to coalesce.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2004-11-08 02:25:40 +00:00
parent 9f54791d54
commit 676dee6ae9
2 changed files with 10 additions and 0 deletions
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8
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -502,6 +502,10 @@ unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
unsigned Reg = makeAnotherReg(V->getType());
copyConstantToRegister(MBB, IPt, C, Reg);
return Reg;
} else if (CastInst *CI = dyn_cast<CastInst>(V)) {
// Do not emit noop casts at all, unless it's a double -> float cast.
if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
return getReg(CI->getOperand(0), MBB, IPt);
} else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
unsigned Reg = makeAnotherReg(V->getType());
unsigned FI = getFixedSizedAllocaFI(AI);
@ -3129,6 +3133,10 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
unsigned SrcClass = getClassB(Op->getType());
unsigned DestClass = getClassB(CI.getType());
// Noop casts are not emitted: getReg will return the source operand as the
// register to use for any uses of the noop cast.
if (DestClass == SrcClass) return;
// If this is a cast from a 32-bit integer to a Long type, and the only uses
// of the cast are GEP instructions, then the cast does not need to be
// generated explicitly, it will be folded into the GEP.

2
lib/Target/PowerPC/README.txt
View File

@ -1,4 +1,6 @@
TODO:
* poor switch statement codegen
* load/store to alloca'd array or struct.
* implement not-R0 register GPR class
* implement scheduling info
* implement do-loop pass