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ARM: Handle physreg targets in RegPair hints gracefully
Register coalescing can change the target of a RegPair hint to a physreg, we should not crash on this. This also slightly improved the way ARMBaseRegisterInfo::updateRegAllocHint() works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233987 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -245,11 +245,15 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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// This register should preferably be even (Odd == 0) or odd (Odd == 1).
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// Check if the other part of the pair has already been assigned, and provide
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// the paired register as the first hint.
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unsigned Paired = Hint.second;
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if (Paired == 0)
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return;
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unsigned PairedPhys = 0;
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if (VRM && VRM->hasPhys(Hint.second)) {
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PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
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if (PairedPhys && MRI.isReserved(PairedPhys))
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PairedPhys = 0;
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if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
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PairedPhys = Paired;
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} else if (VRM && VRM->hasPhys(Paired)) {
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PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
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}
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// First prefer the paired physreg.
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@ -284,9 +288,14 @@ ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
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// change.
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unsigned OtherReg = Hint.second;
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Hint = MRI->getRegAllocationHint(OtherReg);
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if (Hint.second == Reg)
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// Make sure the pair has not already divorced.
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// Make sure the pair has not already divorced.
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if (Hint.second == Reg) {
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MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
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if (TargetRegisterInfo::isVirtualRegister(NewReg))
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MRI->setRegAllocationHint(NewReg,
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Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
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: ARMRI::RegPairOdd, OtherReg);
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}
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}
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}
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22
test/CodeGen/ARM/regpair_hint_phys.ll
Normal file
22
test/CodeGen/ARM/regpair_hint_phys.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llc -o - %s
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; ARM target used to fail an assertion if RegPair{Odd|Even} hint pointed to a
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; physreg.
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7-apple-tvos8.3.0"
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declare i8* @llvm.frameaddress(i32) #1
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declare i8* @llvm.returnaddress(i32) #1
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@somevar = global [2 x i32] [i32 0, i32 0]
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define void @__ubsan_handle_shift_out_of_bounds() #0 {
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entry:
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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%1 = ptrtoint i8* %0 to i32
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%2 = tail call i8* @llvm.returnaddress(i32 0)
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%3 = ptrtoint i8* %2 to i32
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%val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0
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%val1 = insertvalue [2 x i32] %val0, i32 %1, 1
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store [2 x i32] %val1, [2 x i32]* @somevar, align 8
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ret void
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}
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