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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44596 91177308-0d34-0410-b5e6-96231b3b80d8
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Scott Michel
parent
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449
lib/Target/CellSPU/CellSDKIntrinsics.td
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449
lib/Target/CellSPU/CellSDKIntrinsics.td
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//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by a team from the Computer Systems Research
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// Department at The Aerospace Corporation.
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//
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// See README.txt for details.
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//===----------------------------------------------------------------------===//
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///--==-- Arithmetic ops intrinsics --==--
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def CellSDKah:
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RR_Int_v8i16<0b00010011000, "ah", IntegerOp, int_spu_si_ah>;
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def CellSDKahi:
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RI10_Int_v8i16<0b00010011000, "ahi", IntegerOp, int_spu_si_ahi>;
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def CellSDKa:
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RR_Int_v4i32<0b00000011000, "a", IntegerOp, int_spu_si_a>;
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def CellSDKai:
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RI10_Int_v4i32<0b00111000, "ai", IntegerOp, int_spu_si_ai>;
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def CellSDKsfh:
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RR_Int_v8i16<0b00010010000, "sfh", IntegerOp, int_spu_si_sfh>;
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def CellSDKsfhi:
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RI10_Int_v8i16<0b10110000, "sfhi", IntegerOp, int_spu_si_sfhi>;
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def CellSDKsf:
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RR_Int_v4i32<0b00000010000, "sf", IntegerOp, int_spu_si_sf>;
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def CellSDKsfi:
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RI10_Int_v4i32<0b00110000, "sfi", IntegerOp, int_spu_si_sfi>;
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def CellSDKaddx:
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RR_Int_v4i32<0b00000010110, "addx", IntegerOp, int_spu_si_addx>;
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def CellSDKcg:
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RR_Int_v4i32<0b0100001100, "cg", IntegerOp, int_spu_si_cg>;
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def CellSDKcgx:
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RR_Int_v4i32<0b01000010110, "cgx", IntegerOp, int_spu_si_cgx>;
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def CellSDKsfx:
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RR_Int_v4i32<0b10000010110, "sfx", IntegerOp, int_spu_si_sfx>;
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def CellSDKbg:
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RR_Int_v4i32<0b01000010000, "bg", IntegerOp, int_spu_si_bg>;
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def CellSDKbgx:
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RR_Int_v4i32<0b11000010110, "bgx", IntegerOp, int_spu_si_bgx>;
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def CellSDKmpy:
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RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpy $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKmpyu:
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RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyu $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))] >;
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def CellSDKmpyi:
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RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"mpyi $rT, $rA, $val", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA),
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i16ImmSExt10:$val))]>;
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def CellSDKmpyui:
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RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"mpyui $rT, $rA, $val", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA),
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i16ImmSExt10:$val))]>;
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def CellSDKmpya:
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RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
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"mpya $rT, $rA, $rB, $rC", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB),
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(v8i16 VECREG:$rC)))]>;
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def CellSDKmpyh:
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RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyh $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKmpys:
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RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpys $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKmpyhh:
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RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyhh $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKmpyhha:
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RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyhha $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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// Not sure how to match a (set $rT, (add $rT (mpyhh $rA, $rB)))... so leave
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// as an intrinsic for the time being
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def CellSDKmpyhhu:
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RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyhhu $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhu (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKmpyhhau:
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RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"mpyhhau $rT, $rA, $rB", IntegerMulDiv,
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[(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhau (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))]>;
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def CellSDKand:
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RRForm<0b1000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"add\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKandc:
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RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"addc\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_andc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKandbi:
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RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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"andbi\t $rT, $rA, $val", BranchResolv,
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[(set (v16i8 VECREG:$rT),
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(int_spu_si_andbi (v16i8 VECREG:$rA), immU8:$val))]>;
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def CellSDKandhi:
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RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"andhi\t $rT, $rA, $val", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_andhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
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def CellSDKandi:
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RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"andi\t $rT, $rA, $val", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_andi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
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def CellSDKor:
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RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"or\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKorc:
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RRForm<0b10010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"addc\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_orc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKorbi:
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RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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"orbi\t $rT, $rA, $val", BranchResolv,
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[(set (v16i8 VECREG:$rT),
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(int_spu_si_orbi (v16i8 VECREG:$rA), immU8:$val))]>;
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def CellSDKorhi:
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RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"orhi\t $rT, $rA, $val", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_orhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
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def CellSDKori:
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RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"ori\t $rT, $rA, $val", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_ori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
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def CellSDKxor:
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RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"xor\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKxorbi:
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RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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"xorbi\t $rT, $rA, $val", BranchResolv,
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[(set (v16i8 VECREG:$rT), (int_spu_si_xorbi (v16i8 VECREG:$rA), immU8:$val))]>;
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def CellSDKxorhi:
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RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"xorhi\t $rT, $rA, $val", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_xorhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
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def CellSDKxori:
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RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"xori\t $rT, $rA, $val", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_xori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
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def CellSDKnor:
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RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nor\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_nor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKnand:
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RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"nand\t $rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_nand (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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//===----------------------------------------------------------------------===//
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// Shift/rotate intrinsics:
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//===----------------------------------------------------------------------===//
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def CellSDKshli:
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Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val),
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(SHLIv4i32 VECREG:$rA, uimm7:$val)>;
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def CellSDKshlqbi:
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Pat<(int_spu_si_shlqbi VECREG:$rA, VECREG:$rB),
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(SHLQBIvec VECREG:$rA, VECREG:$rB)>;
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def CellSDKshlqii:
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Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
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(SHLQBIIvec VECREG:$rA, uimm7:$val)>;
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def CellSDKshlqby:
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Pat<(int_spu_si_shlqby VECREG:$rA, VECREG:$rB),
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(SHLQBYvec VECREG:$rA, VECREG:$rB)>;
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def CellSDKshlqbyi:
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Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
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(SHLQBYIvec VECREG:$rA, uimm7:$val)>;
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//===----------------------------------------------------------------------===//
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// Branch/compare intrinsics:
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//===----------------------------------------------------------------------===//
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def CellSDKceq:
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RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"ceq\t $rT, $rA, $rB", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_ceq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKceqi:
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RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"ceqi\t $rT, $rA, $val", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_ceqi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
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def CellSDKceqb:
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RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"ceqb\t $rT, $rA, $rB", BranchResolv,
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[(set (v16i8 VECREG:$rT),
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(int_spu_si_ceqb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
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def CellSDKceqbi:
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RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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"ceqbi\t $rT, $rA, $val", BranchResolv,
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[(set (v16i8 VECREG:$rT), (int_spu_si_ceqbi (v16i8 VECREG:$rA), immU8:$val))]>;
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def CellSDKceqh:
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RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"ceqh\t $rT, $rA, $rB", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_ceqh (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
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def CellSDKceqhi:
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RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"ceqhi\t $rT, $rA, $val", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_ceqhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
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def CellSDKcgth:
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RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"cgth\t $rT, $rA, $rB", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_cgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
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def CellSDKcgthi:
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RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"cgthi\t $rT, $rA, $val", BranchResolv,
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[(set (v8i16 VECREG:$rT),
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(int_spu_si_cgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
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def CellSDKcgt:
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RRForm<0b00000010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"cgt\t $rT, $rA, $rB", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_cgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def CellSDKcgti:
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RI10Form<0b00110010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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"cgti\t $rT, $rA, $val", BranchResolv,
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[(set (v4i32 VECREG:$rT),
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(int_spu_si_cgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
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def CellSDKcgtb:
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RRForm<0b00001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"cgtb\t $rT, $rA, $rB", BranchResolv,
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[(set (v16i8 VECREG:$rT),
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(int_spu_si_cgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
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def CellSDKcgtbi:
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RI10Form<0b01110010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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"cgtbi\t $rT, $rA, $val", BranchResolv,
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[(set (v16i8 VECREG:$rT), (int_spu_si_cgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
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def CellSDKclgth:
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RRForm<0b00010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"clgth\t $rT, $rA, $rB", BranchResolv,
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[(set (v8i16 VECREG:$rT),
|
||||
(int_spu_si_clgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKclgthi:
|
||||
RI10Form<0b10111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
|
||||
"clgthi\t $rT, $rA, $val", BranchResolv,
|
||||
[(set (v8i16 VECREG:$rT),
|
||||
(int_spu_si_clgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
|
||||
|
||||
def CellSDKclgt:
|
||||
RRForm<0b00000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"clgt\t $rT, $rA, $rB", BranchResolv,
|
||||
[(set (v4i32 VECREG:$rT),
|
||||
(int_spu_si_clgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKclgti:
|
||||
RI10Form<0b00111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
|
||||
"clgti\t $rT, $rA, $val", BranchResolv,
|
||||
[(set (v4i32 VECREG:$rT),
|
||||
(int_spu_si_clgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
|
||||
|
||||
def CellSDKclgtb:
|
||||
RRForm<0b00001011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"clgtb\t $rT, $rA, $rB", BranchResolv,
|
||||
[(set (v16i8 VECREG:$rT),
|
||||
(int_spu_si_clgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKclgtbi:
|
||||
RI10Form<0b01111010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
|
||||
"clgtbi\t $rT, $rA, $val", BranchResolv,
|
||||
[(set (v16i8 VECREG:$rT),
|
||||
(int_spu_si_clgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating-point intrinsics:
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def CellSDKfa:
|
||||
RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fa\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fa (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfs:
|
||||
RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fs\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fs (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfm:
|
||||
RRForm<0b01100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fm\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fm (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfceq:
|
||||
RRForm<0b01000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fceq\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fceq (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfcgt:
|
||||
RRForm<0b01000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fcgt\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fcgt (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfcmeq:
|
||||
RRForm<0b01010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fcmeq\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fcmeq (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfcmgt:
|
||||
RRForm<0b01010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"fcmgt\t $rT, $rA, $rB", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fcmgt (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKfma:
|
||||
RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
|
||||
"fma\t $rT, $rA, $rB, $rC", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fma (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB),
|
||||
(v4f32 VECREG:$rC)))]>;
|
||||
|
||||
def CellSDKfnms:
|
||||
RRRForm<0b1011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
|
||||
"fnms\t $rT, $rA, $rB, $rC", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fnms (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB),
|
||||
(v4f32 VECREG:$rC)))]>;
|
||||
|
||||
def CellSDKfms:
|
||||
RRRForm<0b1111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
|
||||
"fms\t $rT, $rA, $rB, $rC", SPrecFP,
|
||||
[(set (v4f32 VECREG:$rT), (int_spu_si_fms (v4f32 VECREG:$rA),
|
||||
(v4f32 VECREG:$rB),
|
||||
(v4f32 VECREG:$rC)))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Double precision floating-point intrinsics:
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def CellSDKdfa:
|
||||
RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfa\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfa (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfs:
|
||||
RRForm<0b10110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfs\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfs (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfm:
|
||||
RRForm<0b01110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfm\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfm (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfma:
|
||||
RRForm<0b00111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfma\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfma (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfnma:
|
||||
RRForm<0b11111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfnma\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfnma (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfnms:
|
||||
RRForm<0b01111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfnms\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfnms (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
|
||||
def CellSDKdfms:
|
||||
RRForm<0b10111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
|
||||
"dfms\t $rT, $rA, $rB", DPrecFP,
|
||||
[(set (v2f64 VECREG:$rT), (int_spu_si_dfms (v2f64 VECREG:$rA),
|
||||
(v2f64 VECREG:$rB)))]>;
|
||||
20
lib/Target/CellSPU/SPURegisterNames.h
Normal file
20
lib/Target/CellSPU/SPURegisterNames.h
Normal file
@ -0,0 +1,20 @@
|
||||
//==-- SPURegisterNames.h - Wrapper header for SPU register names -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by a team from the Computer Systems Research
|
||||
// Department at The Aerospace Corporation.
|
||||
//
|
||||
// See README.txt for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#if !defined(SPU_REGISTER_NAMES_H)
|
||||
|
||||
// Define symbolic names for Cell registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "SPUGenRegisterNames.inc"
|
||||
|
||||
#define SPU_REGISTER_NAMES_H 1
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user