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depend more on legalize putting constants on the RHS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
ec151361ba
commit
694c29831a
@ -912,7 +912,6 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
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case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
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}
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//FIXME: check for constant 0.0
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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@ -954,21 +953,12 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
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void AlphaISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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{
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unsigned opcode = N.getOpcode();
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if (opcode == ISD::ADD) {
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
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{ //Normal imm add
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Reg = SelectExpr(N.getOperand(0));
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offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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return;
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}
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else if(N.getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 32767)
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{
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Reg = SelectExpr(N.getOperand(1));
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offset = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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return;
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}
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if (opcode == ISD::ADD && N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
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{ //Normal imm add
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Reg = SelectExpr(N.getOperand(0));
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offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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return;
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}
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Reg = SelectExpr(N);
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offset = 0;
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@ -990,21 +980,17 @@ void AlphaISel::SelectBranchCC(SDOperand N)
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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//Dropping the CC is only useful if we are comparing to 0
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bool LeftZero = SetCC->getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0;
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bool RightZero = SetCC->getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0;
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bool isNE = false;
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//Fix up CC
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ISD::CondCode cCode= SetCC->getCondition();
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if (LeftZero && !RightZero) //Swap Operands
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cCode = ISD::getSetCCSwappedOperands(cCode);
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if(cCode == ISD::SETNE)
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isNE = true;
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if (LeftZero || RightZero) {
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if (RightZero) {
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switch (cCode) {
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default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = Alpha::BEQ; break;
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@ -1018,11 +1004,7 @@ void AlphaISel::SelectBranchCC(SDOperand N)
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case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
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case ISD::SETNE: Opc = Alpha::BNE; break;
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}
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unsigned Tmp1;
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if(LeftZero && !RightZero) //swap Operands
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Tmp1 = SelectExpr(SetCC->getOperand(1)); //Cond
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else
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Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
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unsigned Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
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BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
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return;
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} else {
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@ -1788,37 +1770,30 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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{
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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bool isConst1 = false;
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bool isConst2 = false;
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bool isConst = false;
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int dir;
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//Tmp1 = SelectExpr(N.getOperand(0));
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if(N.getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
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isConst1 = true;
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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isConst2 = true;
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isConst = true;
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=0; break;
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case ISD::SETEQ:
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Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
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case ISD::SETLT:
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Opc = isConst2 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
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Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
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case ISD::SETLE:
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Opc = isConst2 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
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case ISD::SETGT:
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Opc = isConst1 ? Alpha::CMPLTi : Alpha::CMPLT; dir = 2; break;
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case ISD::SETGE:
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Opc = isConst1 ? Alpha::CMPLEi : Alpha::CMPLE; dir = 2; break;
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Opc = isConst ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
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case ISD::SETGT: Opc = Alpha::CMPLT; dir = 2; break;
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case ISD::SETGE: Opc = Alpha::CMPLE; dir = 2; break;
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case ISD::SETULT:
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Opc = isConst2 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
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case ISD::SETUGT:
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Opc = isConst1 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 2; break;
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Opc = isConst ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
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case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 2; break;
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case ISD::SETULE:
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Opc = isConst2 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
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case ISD::SETUGE:
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Opc = isConst1 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 2; break;
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Opc = isConst ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
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case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 2; break;
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case ISD::SETNE: {//Handle this one special
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//std::cerr << "Alpha does not have a setne.\n";
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//abort();
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@ -1835,36 +1810,17 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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if (dir == 1) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isConst2) {
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if (isConst) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} else if (dir == 2) {
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} else { //if (dir == 2) {
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Tmp1 = SelectExpr(N.getOperand(1));
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if (isConst1) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp2 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} else { //dir == 0
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if (isConst1) {
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Tmp1 = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp2).addImm(Tmp1);
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} else if (isConst2) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Alpha::CMPEQi, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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Tmp2 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} else {
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//do the comparison
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@ -2189,27 +2145,16 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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//Int SetCC -> Select
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//Dropping the CC is only useful if we are comparing to 0
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if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0) ||
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(SetCC->getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0))
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cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0))
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{
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//figure out a few things
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bool LeftZero = SetCC->getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0;
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bool RightZero = SetCC->getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0;
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bool LeftConst = N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255;
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bool RightConst = N.getOperand(2).getOpcode() == ISD::Constant &&
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bool useImm = N.getOperand(2).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(2))->getValue() <= 255;
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bool useImm = LeftConst || RightConst;
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//Fix up CC
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ISD::CondCode cCode= SetCC->getCondition();
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if (RightConst && !LeftConst) //Invert sense to get Imm field right
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if (useImm) //Invert sense to get Imm field right
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cCode = ISD::getSetCCInverse(cCode, true);
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if (LeftZero && !RightZero) //Swap Operands
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cCode = ISD::getSetCCSwappedOperands(cCode);
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//Choose the CMOV
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switch (cCode) {
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@ -2225,17 +2170,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
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case ISD::SETNE: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE; break;
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}
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if(LeftZero && !RightZero) //swap Operands
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Tmp1 = SelectExpr(SetCC->getOperand(1)); //Cond
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else
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Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
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Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
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if (LeftConst) {
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Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
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BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
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.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue())
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.addReg(Tmp1);
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} else if (RightConst) {
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if (useImm) {
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Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
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BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
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.addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
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