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Some instructions are passed to the assembler to be

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transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter 2012-08-28 19:07:39 +00:00
parent c6c2ced384
commit 69dba7e204
2 changed files with 28 additions and 21 deletions
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44
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -58,33 +58,37 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
// Direct object specific instruction lowering
if (!OutStreamer.hasRawTextSupport())
switch (MI->getOpcode()) {
case Mips::DSLL:
case Mips::DSRL:
case Mips::DSRA:
assert(MI->getNumOperands() == 3 &&
"Invalid no. of machine operands for shift!");
assert(MI->getOperand(2).isImm());
int64_t Shift = MI->getOperand(2).getImm();
if (Shift > 31) {
MCInst TmpInst0;
MCInstLowering.LowerLargeShift(MI, TmpInst0, Shift - 32);
OutStreamer.EmitInstruction(TmpInst0);
return;
}
break;
}
MachineBasicBlock::const_instr_iterator I = MI;
MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
do {
MCInst TmpInst0;
// Direct object specific instruction lowering
if (!OutStreamer.hasRawTextSupport())
switch (I->getOpcode()) {
// If shift amount is >= 32 it the inst needs to be lowered further
case Mips::DSLL:
case Mips::DSRL:
case Mips::DSRA:
{
assert(I->getNumOperands() == 3 &&
"Invalid no. of machine operands for shift!");
assert(I->getOperand(2).isImm());
int64_t Shift = I->getOperand(2).getImm();
if (Shift > 31) {
MCInst TmpInst0;
MCInstLowering.LowerLargeShift(I, TmpInst0, Shift - 32);
OutStreamer.EmitInstruction(TmpInst0);
return;
}
}
}
MCInstLowering.Lower(I++, TmpInst0);
OutStreamer.EmitInstruction(TmpInst0);
} while ((I != E) && I->isInsideBundle());
} while ((I != E) && I->isInsideBundle()); // Delay slot check
}
//===----------------------------------------------------------------------===//

5
test/MC/Mips/mips64shift.ll
View File

@ -1,5 +1,8 @@
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry: