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Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl
in order to fold it into a load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4120,6 +4120,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// we can fold the truncate through the shift.
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unsigned ShLeftAmt = 0;
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if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
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ExtVT == VT &&
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TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
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if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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ShLeftAmt = N01->getZExtValue();
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@ -1,12 +1,11 @@
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; RUN: llc -march=x86-64 < %s
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; DAGCombiner should fold this code in finite time.
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; rdar://8606584
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; RUN: llc -march=x86-64 < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-pc-linux-gnu"
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; DAGCombiner should fold this code in finite time.
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; rdar://8606584
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define void @D() nounwind readnone {
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bb.nph:
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br label %while.cond
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@ -30,3 +29,37 @@ while.cond: ; preds = %while.cond, %bb.nph
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while.end: ; preds = %while.cond
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ret void
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}
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; DAGCombiner shouldn't fold the sdiv (ashr) away.
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; rdar://8636812
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; CHECK: main:
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; CHECK: sarl
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define i32 @main() nounwind {
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entry:
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%i = alloca i32, align 4
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%j = alloca i8, align 1
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store i32 127, i32* %i, align 4
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store i8 0, i8* %j, align 1
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%tmp3 = load i32* %i, align 4
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%mul = mul nsw i32 %tmp3, 2
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%conv4 = trunc i32 %mul to i8
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%conv5 = sext i8 %conv4 to i32
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%div6 = sdiv i32 %conv5, 2
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%conv7 = trunc i32 %div6 to i8
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%conv9 = sext i8 %conv7 to i32
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%cmp = icmp eq i32 %conv9, -1
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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ret i32 0
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if.end: ; preds = %entry
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call void @abort() noreturn
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unreachable
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}
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declare void @abort() noreturn
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declare void @exit(i32) noreturn
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