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Further cleanups and simplifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9282 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1574,30 +1574,19 @@ void ISel::visitLoadInst(LoadInst &I) {
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unsigned DestReg = getReg(I);
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unsigned DestReg = getReg(I);
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unsigned Class = getClassB(I.getType());
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unsigned Class = getClassB(I.getType());
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switch (Class) {
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case cFP: {
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if (Class == cLong) {
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MachineBasicBlock::iterator MBBI = BB->end();
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addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
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assert(I.getType() == Type::FloatTy || I.getType() == Type::DoubleTy &&
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addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
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"Unknown FP type!");
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unsigned Opc = I.getType() == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
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addDirectMem(BMI(BB, MBBI, Opc, 4, DestReg), SrcAddrReg);
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return;
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return;
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}
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}
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case cLong: case cInt: case cShort: case cByte:
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break; // Integers of various sizes handled below
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default: assert(0 && "Unknown memory class!");
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}
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unsigned IReg = DestReg;
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static const unsigned Opcodes[] = {
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X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
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static const unsigned Opcode[] = {
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X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
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};
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};
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addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
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unsigned Opcode = Opcodes[Class];
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if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
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// Handle long values now...
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addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
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if (Class == cLong)
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addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
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}
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}
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/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
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/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
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@ -1609,23 +1598,19 @@ void ISel::visitStoreInst(StoreInst &I) {
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const Type *ValTy = I.getOperand(0)->getType();
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const Type *ValTy = I.getOperand(0)->getType();
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unsigned Class = getClassB(ValTy);
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unsigned Class = getClassB(ValTy);
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switch (Class) {
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case cLong:
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if (Class == cLong) {
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addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
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addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
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addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
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addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
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return;
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return;
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case cFP: {
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unsigned StoreOpcode = ValTy == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
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addDirectMem(BuildMI(BB, StoreOpcode, 5), AddressReg).addReg(ValReg);
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return;
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}
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case cInt: case cShort: case cByte:
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break; // Integers of various sizes handled below
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default: assert(0 && "Unknown memory class!");
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}
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}
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static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
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static const unsigned Opcodes[] = {
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addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
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X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
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};
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unsigned Opcode = Opcodes[Class];
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if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
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addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
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}
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}
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@ -1574,30 +1574,19 @@ void ISel::visitLoadInst(LoadInst &I) {
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unsigned DestReg = getReg(I);
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unsigned DestReg = getReg(I);
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unsigned Class = getClassB(I.getType());
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unsigned Class = getClassB(I.getType());
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switch (Class) {
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case cFP: {
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if (Class == cLong) {
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MachineBasicBlock::iterator MBBI = BB->end();
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addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
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assert(I.getType() == Type::FloatTy || I.getType() == Type::DoubleTy &&
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addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
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"Unknown FP type!");
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unsigned Opc = I.getType() == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
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addDirectMem(BMI(BB, MBBI, Opc, 4, DestReg), SrcAddrReg);
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return;
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return;
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}
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}
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case cLong: case cInt: case cShort: case cByte:
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break; // Integers of various sizes handled below
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default: assert(0 && "Unknown memory class!");
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}
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unsigned IReg = DestReg;
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static const unsigned Opcodes[] = {
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X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
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static const unsigned Opcode[] = {
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X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
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};
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};
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addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
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unsigned Opcode = Opcodes[Class];
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if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
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// Handle long values now...
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addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
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if (Class == cLong)
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addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
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}
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}
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/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
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/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
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@ -1609,23 +1598,19 @@ void ISel::visitStoreInst(StoreInst &I) {
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const Type *ValTy = I.getOperand(0)->getType();
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const Type *ValTy = I.getOperand(0)->getType();
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unsigned Class = getClassB(ValTy);
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unsigned Class = getClassB(ValTy);
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switch (Class) {
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case cLong:
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if (Class == cLong) {
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addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
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addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
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addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
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addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
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return;
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return;
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case cFP: {
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unsigned StoreOpcode = ValTy == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
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addDirectMem(BuildMI(BB, StoreOpcode, 5), AddressReg).addReg(ValReg);
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return;
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}
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case cInt: case cShort: case cByte:
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break; // Integers of various sizes handled below
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default: assert(0 && "Unknown memory class!");
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}
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}
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static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
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static const unsigned Opcodes[] = {
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addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
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X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
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};
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unsigned Opcode = Opcodes[Class];
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if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
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addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
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}
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}
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