From 6ac614a4f274bab9f08f70fda86aeb711952e828 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 13 Apr 2005 02:41:52 +0000 Subject: [PATCH] Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing things like this: mov r9 = 65535;; and r8 = r8, r9;; To be emitted instead of: zxt2 r8 = r8;; To get this back, the selector for ISD::AND should recognize this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21269 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/IA64/IA64ISelPattern.cpp | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 5a743996ae7..c2623d020cf 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -1304,23 +1304,6 @@ pC = pA OR pB return Result; } - case ISD::ZERO_EXTEND_INREG: { - Tmp1 = SelectExpr(N.getOperand(0)); - MVTSDNode* MVN = dyn_cast(Node); - switch(MVN->getExtraValueType()) - { - default: - Node->dump(); - assert(0 && "don't know how to zero extend this type"); - break; - case MVT::i8: Opc = IA64::ZXT1; break; - case MVT::i16: Opc = IA64::ZXT2; break; - case MVT::i32: Opc = IA64::ZXT4; break; - } - BuildMI(BB, Opc, 1, Result).addReg(Tmp1); - return Result; - } - case ISD::SIGN_EXTEND_INREG: { Tmp1 = SelectExpr(N.getOperand(0)); MVTSDNode* MVN = dyn_cast(Node);