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AMDGPU: Run pointer optimization passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
cf9e0af1ce
commit
6af03e5068
@ -36,7 +36,8 @@
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include <llvm/CodeGen/Passes.h>
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#include "llvm/Transforms/Scalar/GVN.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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@ -180,8 +181,9 @@ public:
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return nullptr;
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}
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void addEarlyCSEOrGVNPass();
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void addStraightLineScalarOptimizationPasses();
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void addIRPasses() override;
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void addCodeGenPrepare() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addGCPasses() override;
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@ -225,6 +227,29 @@ TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
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});
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}
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void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
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if (getOptLevel() == CodeGenOpt::Aggressive)
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addPass(createGVNPass());
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else
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addPass(createEarlyCSEPass());
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}
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void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
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addPass(createSeparateConstOffsetFromGEPPass());
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addPass(createSpeculativeExecutionPass());
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// ReassociateGEPs exposes more opportunites for SLSR. See
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// the example in reassociate-geps-and-slsr.ll.
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addPass(createStraightLineStrengthReducePass());
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// SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
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// EarlyCSE can reuse.
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addEarlyCSEOrGVNPass();
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// Run NaryReassociate after EarlyCSE/GVN to be more effective.
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addPass(createNaryReassociatePass());
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// NaryReassociate on GEPs creates redundant common expressions, so run
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// EarlyCSE after it.
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addPass(createEarlyCSEPass());
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}
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void AMDGPUPassConfig::addIRPasses() {
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// There is no reason to run these.
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disablePass(&StackMapLivenessID);
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@ -244,17 +269,31 @@ void AMDGPUPassConfig::addIRPasses() {
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// Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
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addPass(createAMDGPUOpenCLImageTypeLoweringPass());
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TargetPassConfig::addIRPasses();
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}
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void AMDGPUPassConfig::addCodeGenPrepare() {
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const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
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const AMDGPUSubtarget &ST = *TM.getSubtargetImpl();
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if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) {
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addPass(createAMDGPUPromoteAlloca(&TM));
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addPass(createSROAPass());
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}
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TargetPassConfig::addCodeGenPrepare();
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addStraightLineScalarOptimizationPasses();
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TargetPassConfig::addIRPasses();
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// EarlyCSE is not always strong enough to clean up what LSR produces. For
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// example, GVN can combine
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//
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// %0 = add %a, %b
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// %1 = add %b, %a
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//
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// and
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//
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// %0 = shl nsw %a, 2
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// %1 = shl %a, 2
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//
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// but EarlyCSE can do neither of them.
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if (getOptLevel() != CodeGenOpt::None)
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addEarlyCSEOrGVNPass();
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}
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bool
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@ -1,6 +1,6 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI %s
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; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=CI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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@ -12,15 +12,14 @@
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; GCN: .long 47180
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; GCN-NEXT: .long 32900
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; EG: {{^}}local_memory_two_objects:
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; FUNC-LABEL: {{^}}local_memory_two_objects:
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; We would like to check the lds writes are using different
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; addresses, but due to variations in the scheduler, we can't do
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; this consistently on evergreen GPUs.
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; EG: LDS_WRITE
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; EG: LDS_WRITE
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; GCN: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
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; GCN-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]]
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; GROUP_BARRIER must be the last instruction in a clause
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; EG: GROUP_BARRIER
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@ -30,9 +29,29 @@
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; constant offsets.
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; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
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; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
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; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
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; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:4
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; GCN: v_lshlrev_b32_e32 [[ADDRW:v[0-9]+]], 2, v0
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; CI-DAG: ds_write_b32 [[ADDRW]], {{v[0-9]*}} offset:16
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; CI-DAG: ds_write_b32 [[ADDRW]], {{v[0-9]*$}}
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; SI: v_add_i32_e32 [[ADDRW_OFF:v[0-9]+]], vcc, 16, [[ADDRW]]
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; SI-DAG: ds_write_b32 [[ADDRW]],
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; SI-DAG: ds_write_b32 [[ADDRW_OFF]],
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; GCN: s_barrier
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; SI-DAG: v_sub_i32_e32 [[SUB0:v[0-9]+]], vcc, 28, [[ADDRW]]
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; SI-DAG: v_sub_i32_e32 [[SUB1:v[0-9]+]], vcc, 12, [[ADDRW]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB0]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB1]]
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; CI: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, 0, [[ADDRW]]
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; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, [[SUB]] offset0:3 offset1:7
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define void @local_memory_two_objects(i32 addrspace(1)* %out) {
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entry:
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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@ -223,7 +223,7 @@ define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
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; EG: MIN_UINT
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define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%b = load i32, i32 addrspace(1)* %aptr, align 4
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%b = load i32, i32 addrspace(1)* %bptr, align 4
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%cmp = icmp ult i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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@ -1,27 +1,27 @@
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; RUN: llc < %s -march=r600 -mattr=disable-irstructurizer -mcpu=redwood | FileCheck %s
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; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -mattr=disable-irstructurizer -mcpu=redwood < %s | FileCheck %s
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; These tests make sure the compiler is optimizing branches using predicates
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; when it is legal to do so.
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; CHECK: {{^}}simple_if:
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; CHECK-LABEL: {{^}}simple_if:
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; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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define void @simple_if(i32 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = icmp sgt i32 %in, 0
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br i1 %0, label %IF, label %ENDIF
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%cmp0 = icmp sgt i32 %in, 0
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br i1 %cmp0, label %IF, label %ENDIF
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IF:
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%1 = shl i32 %in, 1
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%tmp1 = shl i32 %in, 1
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br label %ENDIF
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ENDIF:
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%2 = phi i32 [ %in, %entry ], [ %1, %IF ]
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store i32 %2, i32 addrspace(1)* %out
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%tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ]
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}simple_if_else:
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; CHECK-LABEL: {{^}}simple_if_else:
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; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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@ -44,7 +44,7 @@ ENDIF:
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ret void
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}
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; CHECK: {{^}}nested_if:
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; CHECK-LABEL: {{^}}nested_if:
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; CHECK: ALU_PUSH_BEFORE
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; CHECK: JUMP
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; CHECK: POP
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@ -71,7 +71,7 @@ ENDIF:
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ret void
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}
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; CHECK: {{^}}nested_if_else:
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; CHECK-LABEL: {{^}}nested_if_else:
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; CHECK: ALU_PUSH_BEFORE
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; CHECK: JUMP
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; CHECK: POP
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@ -1,4 +1,4 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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@ -36,38 +36,6 @@ define void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
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ret void
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}
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; This really folds away to false
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; FUNC-LABEL: {{^}}sext_bool_icmp_eq_1:
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; GCN: v_cmp_eq_i32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
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; GCN-NEXT: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
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; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
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; GCN-NEXT: buffer_store_byte [[TMP]]
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; GCN-NEXT: s_endpgm
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define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp eq i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp eq i32 %ext, 1
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; This really folds away to true
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_1:
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; GCN: v_cmp_ne_i32_e32 vcc,
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; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
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; GCN-NEXT: v_cmp_ne_i32_e32 vcc, 1, [[TMP]]{{$}}
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; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
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; GCN-NEXT: buffer_store_byte [[TMP]]
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; GCN-NEXT: s_endpgm
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define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp ne i32 %ext, 1
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sext_bool_icmp_eq_neg1:
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; GCN-NOT: v_cmp
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; GCN: v_cmp_eq_i32_e32 vcc,
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@ -177,24 +145,6 @@ define void @zext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounw
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ret void
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}
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_k:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; VI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; VI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
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; GCN: v_cmp_ne_i32_e32 vcc, 2, [[VB]]{{$}}
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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; GCN: buffer_store_byte
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; GCN: s_endpgm
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define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp ne i32 %ext, 2
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}cmp_zext_k_i8max:
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; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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@ -294,3 +244,40 @@ define void @zext_bool_icmp_eq_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; FIXME: These cases should really be able fold to true/false in
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; DAGCombiner
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; This really folds away to false
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; FUNC-LABEL: {{^}}sext_bool_icmp_eq_1:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_byte [[K]]
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define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp eq i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp eq i32 %ext, 1
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_1:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 1{{$}}
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; GCN: buffer_store_byte [[K]]
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define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp ne i32 %ext, 1
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sext_bool_icmp_ne_k:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 1{{$}}
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; GCN: buffer_store_byte [[K]]
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define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = sext i1 %icmp0 to i32
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%icmp1 = icmp ne i32 %ext, 2
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store i1 %icmp1, i1 addrspace(1)* %out
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ret void
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}
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@ -259,16 +259,17 @@ ENDIF: ; preds = %IF, %main_body
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; SI: buffer_store
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; SI: {{^}}[[EXIT]]:
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; SI: s_endpgm
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define void @icmp_users_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
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define void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp1 = icmp sgt i32 %cond, 0
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br i1 %tmp1, label %bb2, label %bb9
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%cmp0 = icmp sgt i32 %cond0, 0
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%cmp1 = icmp sgt i32 %cond1, 0
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br i1 %cmp0, label %bb2, label %bb9
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bb2: ; preds = %bb
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%tmp2 = sext i1 %tmp1 to i32
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%tmp2 = sext i1 %cmp1 to i32
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%tmp3 = add i32 %tmp2, %tmp
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br i1 %tmp1, label %bb9, label %bb7
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br i1 %cmp1, label %bb9, label %bb7
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bb7: ; preds = %bb5
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store i32 %tmp3, i32 addrspace(1)* %out
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@ -76,7 +76,8 @@ bb13:
|
||||
; CHECK: br i1
|
||||
|
||||
; CHECK: bb:
|
||||
; CHECK: getelementptr i8, i8 addrspace(1)* %t, i32 %lsr.iv
|
||||
; CHECK: %idxprom = sext i32 %lsr.iv1 to i64
|
||||
; CHECK: getelementptr i8, i8 addrspace(1)* %t, i64 %idxprom
|
||||
define void @global_gep_user(i32 %arg0) nounwind {
|
||||
entry:
|
||||
br label %bb11
|
||||
|
||||
Loading…
Reference in New Issue
Block a user