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Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
parent
6c1202c459
commit
6afb65c2b7
@ -23,7 +23,6 @@ class AMDGPUTargetMachine;
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// R600 Passes
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FunctionPass* createR600TextureIntrinsicsReplacer();
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FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
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FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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FunctionPass *createR600EmitClauseMarkers(TargetMachine &tm);
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FunctionPass *createR600Packetizer(TargetMachine &tm);
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@ -130,11 +130,6 @@ bool AMDGPUPassConfig::addInstSelector() {
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bool AMDGPUPassConfig::addPreRegAlloc() {
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addPass(createAMDGPUConvertToISAPass(*TM));
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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addPass(createR600VectorRegMerger(*TM));
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}
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return false;
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}
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@ -41,7 +41,6 @@ add_llvm_target(R600CodeGen
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600TextureIntrinsicsReplacer.cpp
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@ -1,363 +0,0 @@
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//===--------------------- R600MergeVectorRegisters.cpp -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass merges inputs of swizzeable instructions into vector sharing
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/// common data and/or have enough undef subreg using swizzle abilities.
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///
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/// For instance let's consider the following pseudo code :
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/// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
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/// ...
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/// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3
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/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
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///
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/// is turned into :
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/// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
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/// ...
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/// vreg7<def> = INSERT_SUBREG vreg4, sub3
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/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
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///
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/// This allow regalloc to reduce register pressure for vector registers and
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/// to reduce MOV count.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "vec-merger"
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#include "llvm/Support/Debug.h"
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#include "AMDGPU.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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static bool
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isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
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for (MachineRegisterInfo::def_iterator It = MRI.def_begin(Reg),
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E = MRI.def_end(); It != E; ++It) {
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return (*It).isImplicitDef();
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}
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llvm_unreachable("Reg without a def");
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return false;
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}
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class RegSeqInfo {
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public:
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MachineInstr *Instr;
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DenseMap<unsigned, unsigned> RegToChan;
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std::vector<unsigned> UndefReg;
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RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
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assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
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for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
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MachineOperand &MO = Instr->getOperand(i);
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unsigned Chan = Instr->getOperand(i + 1).getImm();
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if (isImplicitlyDef(MRI, MO.getReg()))
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UndefReg.push_back(Chan);
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else
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RegToChan[MO.getReg()] = Chan;
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}
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}
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RegSeqInfo() {}
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bool operator==(const RegSeqInfo &RSI) const {
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return RSI.Instr == Instr;
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}
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};
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class R600VectorRegMerger : public MachineFunctionPass {
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private:
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MachineRegisterInfo *MRI;
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const R600InstrInfo *TII;
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bool canSwizzle(const MachineInstr &) const;
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bool areAllUsesSwizzeable(unsigned Reg) const;
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void SwizzleInput(MachineInstr &,
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const std::vector<std::pair<unsigned, unsigned> > &) const;
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bool tryMergeVector(const RegSeqInfo *, RegSeqInfo *,
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std::vector<std::pair<unsigned, unsigned> > &Remap) const;
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bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned> > &RemapChan);
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bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned> > &RemapChan);
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MachineInstr *RebuildVector(RegSeqInfo *MI,
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const RegSeqInfo *BaseVec,
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const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const;
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void RemoveMI(MachineInstr *);
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void trackRSI(const RegSeqInfo &RSI);
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typedef DenseMap<unsigned, std::vector<MachineInstr *> > InstructionSetMap;
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DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
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InstructionSetMap PreviousRegSeqByReg;
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InstructionSetMap PreviousRegSeqByUndefCount;
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public:
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static char ID;
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R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
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TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "R600 Vector Registers Merge Pass";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char R600VectorRegMerger::ID = 0;
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bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
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const {
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if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
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return true;
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switch (MI.getOpcode()) {
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case AMDGPU::R600_ExportSwz:
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case AMDGPU::EG_ExportSwz:
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return true;
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default:
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return false;
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}
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}
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bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
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RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned> > &Remap)
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const {
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unsigned CurrentUndexIdx = 0;
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for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
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E = ToMerge->RegToChan.end(); It != E; ++It) {
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DenseMap<unsigned, unsigned>::const_iterator PosInUntouched =
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Untouched->RegToChan.find((*It).first);
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if (PosInUntouched != Untouched->RegToChan.end()) {
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Remap.push_back(std::pair<unsigned, unsigned>
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((*It).second, (*PosInUntouched).second));
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continue;
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}
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if (CurrentUndexIdx >= Untouched->UndefReg.size())
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return false;
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Remap.push_back(std::pair<unsigned, unsigned>
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((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
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}
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return true;
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}
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MachineInstr *R600VectorRegMerger::RebuildVector(
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RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
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const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
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unsigned Reg = RSI->Instr->getOperand(0).getReg();
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MachineBasicBlock::iterator Pos = RSI->Instr;
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MachineBasicBlock &MBB = *Pos->getParent();
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DebugLoc DL = Pos->getDebugLoc();
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unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
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DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
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std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
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for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
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E = RSI->RegToChan.end(); It != E; ++It) {
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if (BaseRSI->RegToChan.find((*It).first) != BaseRSI->RegToChan.end()) {
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UpdatedRegToChan[(*It).first] = (*It).second;
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continue;
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}
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unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
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unsigned SubReg = (*It).first;
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unsigned Swizzle = (*It).second;
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unsigned Chan;
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for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
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if (RemapChan[j].first == Swizzle) {
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Chan = RemapChan[j].second;
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break;
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}
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}
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MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
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DstReg)
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.addReg(SrcVec)
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.addReg(SubReg)
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.addImm(Chan);
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UpdatedRegToChan[SubReg] = Chan;
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for (std::vector<unsigned>::iterator RemoveIt = UpdatedUndef.begin(),
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RemoveE = UpdatedUndef.end(); RemoveIt != RemoveE; ++ RemoveIt) {
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if (*RemoveIt == Chan)
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UpdatedUndef.erase(RemoveIt);
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}
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DEBUG(dbgs() << " ->"; Tmp->dump(););
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SrcVec = DstReg;
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}
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Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
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.addReg(SrcVec);
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DEBUG(dbgs() << " ->"; Pos->dump(););
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DEBUG(dbgs() << " Updating Swizzle:\n");
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for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg),
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E = MRI->use_end(); It != E; ++It) {
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DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->");
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SwizzleInput(*It, RemapChan);
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DEBUG((*It).dump());
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}
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RSI->Instr->eraseFromParent();
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// Update RSI
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RSI->Instr = Pos;
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RSI->RegToChan = UpdatedRegToChan;
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RSI->UndefReg = UpdatedUndef;
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return Pos;
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}
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void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
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for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
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E = PreviousRegSeqByReg.end(); It != E; ++It) {
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std::vector<MachineInstr *> &MIs = (*It).second;
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MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end());
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}
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for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
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E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
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std::vector<MachineInstr *> &MIs = (*It).second;
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MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end());
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}
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}
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void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
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const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
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unsigned Offset;
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if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
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Offset = 2;
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else
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Offset = 3;
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for (unsigned i = 0; i < 4; i++) {
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unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
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for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
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if (RemapChan[j].first == Swizzle) {
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MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
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break;
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}
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}
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}
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}
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bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
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for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg),
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E = MRI->use_end(); It != E; ++It) {
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if (!canSwizzle(*It))
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return false;
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}
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return true;
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}
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bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
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RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned> > &RemapChan) {
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for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
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MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
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if (!MOp->isReg())
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continue;
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if (PreviousRegSeqByReg[MOp->getReg()].empty())
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continue;
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std::vector<MachineInstr *> MIs = PreviousRegSeqByReg[MOp->getReg()];
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for (unsigned i = 0, e = MIs.size(); i < e; i++) {
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CompatibleRSI = PreviousRegSeq[MIs[i]];
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if (RSI == CompatibleRSI)
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continue;
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if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
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return true;
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}
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}
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return false;
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}
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bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
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RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned> > &RemapChan) {
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unsigned NeededUndefs = 4 - RSI.UndefReg.size();
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if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
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return false;
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std::vector<MachineInstr *> &MIs =
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PreviousRegSeqByUndefCount[NeededUndefs];
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CompatibleRSI = PreviousRegSeq[MIs.back()];
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tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
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return true;
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}
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void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
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for (DenseMap<unsigned, unsigned>::const_iterator
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It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
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PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
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}
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PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
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PreviousRegSeq[RSI.Instr] = RSI;
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}
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bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
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MRI = &(Fn.getRegInfo());
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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MachineBasicBlock *MB = MBB;
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PreviousRegSeq.clear();
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PreviousRegSeqByReg.clear();
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PreviousRegSeqByUndefCount.clear();
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for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
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MII != MIIE; ++MII) {
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MachineInstr *MI = MII;
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if (MI->getOpcode() != AMDGPU::REG_SEQUENCE)
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continue;
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RegSeqInfo RSI(*MRI, MI);
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// All uses of MI are swizzeable ?
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unsigned Reg = MI->getOperand(0).getReg();
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if (!areAllUsesSwizzeable(Reg))
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continue;
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DEBUG (dbgs() << "Trying to optimize ";
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MI->dump();
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);
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RegSeqInfo CandidateRSI;
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std::vector<std::pair<unsigned, unsigned> > RemapChan;
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DEBUG(dbgs() << "Using common slots...\n";);
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if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
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// Remove CandidateRSI mapping
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RemoveMI(CandidateRSI.Instr);
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MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
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trackRSI(RSI);
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continue;
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}
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DEBUG(dbgs() << "Using free slots...\n";);
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RemapChan.clear();
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if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
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RemoveMI(CandidateRSI.Instr);
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MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
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trackRSI(RSI);
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continue;
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}
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//Failed to merge
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trackRSI(RSI);
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}
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}
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return false;
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}
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}
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llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) {
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return new R600VectorRegMerger(tm);
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}
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@ -1,30 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK-NOT: MOV
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define void @test() {
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%1 = call float @llvm.R600.load.input(i32 0)
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%2 = call float @llvm.R600.load.input(i32 1)
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%3 = call float @llvm.R600.load.input(i32 2)
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%4 = call float @llvm.R600.load.input(i32 3)
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%5 = fmul float %1, 3.0
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%6 = fmul float %2, 3.0
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%7 = fmul float %3, 3.0
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%8 = fmul float %4, 3.0
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%9 = insertelement <4 x float> undef, float %5, i32 0
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%10 = insertelement <4 x float> %9, float %6, i32 1
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%11 = insertelement <4 x float> undef, float %7, i32 0
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%12 = insertelement <4 x float> %11, float %5, i32 1
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%13 = insertelement <4 x float> undef, float %8, i32 0
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%14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
%17 = fadd <4 x float> %14, %15
|
||||
%18 = fadd <4 x float> %17, %16
|
||||
call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.R600.load.input(i32) readnone
|
||||
declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
|
||||
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
|
||||
Loading…
Reference in New Issue
Block a user