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X86: Remove TargetMachine CPU auto-detection.
This logic is properly in the realm of whatever is creating the TargetMachine. This makes plain 'llc foo.ll' consistent across heterogenous machines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206094 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
e13b87c08d
commit
6bb00df864
@ -173,241 +173,6 @@ bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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static bool OSHasAVXSupport() {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#else
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int rEAX = 0; // Ensures we return false
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#endif
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return (rEAX & 6) == 6;
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#else
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return false;
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#endif
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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unsigned MaxLevel;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
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MaxLevel < 1)
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return;
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X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
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if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
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if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
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if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
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if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
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if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
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if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
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if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
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if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
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X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
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}
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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if ((ECX >> 1) & 0x1) {
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HasPCLMUL = true;
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ToggleFeature(X86::FeaturePCLMUL);
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}
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if ((ECX >> 12) & 0x1) {
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HasFMA = true;
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ToggleFeature(X86::FeatureFMA);
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}
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if (IsIntel && ((ECX >> 22) & 0x1)) {
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HasMOVBE = true;
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ToggleFeature(X86::FeatureMOVBE);
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}
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if ((ECX >> 23) & 0x1) {
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HasPOPCNT = true;
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ToggleFeature(X86::FeaturePOPCNT);
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}
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if ((ECX >> 25) & 0x1) {
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HasAES = true;
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ToggleFeature(X86::FeatureAES);
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}
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if ((ECX >> 29) & 0x1) {
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HasF16C = true;
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ToggleFeature(X86::FeatureF16C);
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}
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if (IsIntel && ((ECX >> 30) & 0x1)) {
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HasRDRAND = true;
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ToggleFeature(X86::FeatureRDRAND);
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}
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if ((ECX >> 13) & 0x1) {
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HasCmpxchg16b = true;
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ToggleFeature(X86::FeatureCMPXCHG16B);
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}
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if (IsIntel || IsAMD) {
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// Determine if bit test memory instructions are slow.
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unsigned Family = 0;
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unsigned Model = 0;
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X86_MC::DetectFamilyModel(EAX, Family, Model);
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if (IsAMD || (Family == 6 && Model >= 13)) {
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IsBTMemSlow = true;
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ToggleFeature(X86::FeatureSlowBTMem);
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}
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// Determine if SHLD/SHRD instructions have higher latency then the
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// equivalent series of shifts/or instructions.
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// FIXME: Add Intel's processors that have SHLD instructions with very
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// poor latency.
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if (IsAMD) {
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IsSHLDSlow = true;
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ToggleFeature(X86::FeatureSlowSHLD);
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}
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// If it's an Intel chip since Nehalem and not an Atom chip, unaligned
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// memory access is fast. We hard code model numbers here because they
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// aren't strictly increasing for Intel chips it seems.
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if (IsIntel &&
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((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
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// Jasper Froest
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(Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
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(Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
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(Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
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(Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
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(Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
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(Family == 6 && Model == 0x2A) || // SandyBridge
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(Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
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(Family == 6 && Model == 0x3A) || // IvyBridge
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(Family == 6 && Model == 0x3E) || // IvyBridge EP
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(Family == 6 && Model == 0x3C) || // Haswell
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(Family == 6 && Model == 0x3F) || // ...
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(Family == 6 && Model == 0x45) || // ...
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(Family == 6 && Model == 0x46))) { // ...
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IsUAMemFast = true;
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ToggleFeature(X86::FeatureFastUAMem);
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}
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// Set processor type. Currently only Atom or Silvermont (SLM) is detected.
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if (Family == 6 &&
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(Model == 28 || Model == 38 || Model == 39 ||
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Model == 53 || Model == 54)) {
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X86ProcFamily = IntelAtom;
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UseLeaForSP = true;
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ToggleFeature(X86::FeatureLeaForSP);
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}
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else if (Family == 6 &&
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(Model == 55 || Model == 74 || Model == 77)) {
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X86ProcFamily = IntelSLM;
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}
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unsigned MaxExtLevel;
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X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
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if (MaxExtLevel >= 0x80000001) {
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X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 29) & 0x1) {
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HasX86_64 = true;
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ToggleFeature(X86::Feature64Bit);
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}
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if ((ECX >> 5) & 0x1) {
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HasLZCNT = true;
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ToggleFeature(X86::FeatureLZCNT);
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}
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if (IsIntel && ((ECX >> 8) & 0x1)) {
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HasPRFCHW = true;
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ToggleFeature(X86::FeaturePRFCHW);
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}
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if (IsAMD) {
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if ((ECX >> 6) & 0x1) {
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HasSSE4A = true;
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ToggleFeature(X86::FeatureSSE4A);
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}
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if ((ECX >> 11) & 0x1) {
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HasXOP = true;
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ToggleFeature(X86::FeatureXOP);
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}
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if ((ECX >> 16) & 0x1) {
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HasFMA4 = true;
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ToggleFeature(X86::FeatureFMA4);
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}
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}
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}
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}
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if (MaxLevel >= 7) {
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if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
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if (IsIntel && (EBX & 0x1)) {
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HasFSGSBase = true;
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ToggleFeature(X86::FeatureFSGSBase);
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}
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if ((EBX >> 3) & 0x1) {
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HasBMI = true;
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ToggleFeature(X86::FeatureBMI);
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}
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if ((EBX >> 4) & 0x1) {
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HasHLE = true;
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ToggleFeature(X86::FeatureHLE);
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}
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if (IsIntel && ((EBX >> 5) & 0x1)) {
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X86SSELevel = AVX2;
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ToggleFeature(X86::FeatureAVX2);
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}
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if (IsIntel && ((EBX >> 8) & 0x1)) {
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HasBMI2 = true;
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ToggleFeature(X86::FeatureBMI2);
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}
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if (IsIntel && ((EBX >> 11) & 0x1)) {
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HasRTM = true;
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ToggleFeature(X86::FeatureRTM);
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}
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if (IsIntel && ((EBX >> 16) & 0x1)) {
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X86SSELevel = AVX512F;
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ToggleFeature(X86::FeatureAVX512);
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}
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if (IsIntel && ((EBX >> 18) & 0x1)) {
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HasRDSEED = true;
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ToggleFeature(X86::FeatureRDSEED);
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}
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if (IsIntel && ((EBX >> 19) & 0x1)) {
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HasADX = true;
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ToggleFeature(X86::FeatureADX);
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}
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if (IsIntel && ((EBX >> 26) & 0x1)) {
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HasPFI = true;
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ToggleFeature(X86::FeaturePFI);
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}
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if (IsIntel && ((EBX >> 27) & 0x1)) {
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HasERI = true;
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ToggleFeature(X86::FeatureERI);
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}
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if (IsIntel && ((EBX >> 28) & 0x1)) {
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HasCDI = true;
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ToggleFeature(X86::FeatureCDI);
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}
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if (IsIntel && ((EBX >> 29) & 0x1)) {
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HasSHA = true;
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ToggleFeature(X86::FeatureSHA);
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}
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}
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if (IsAMD && ((ECX >> 21) & 0x1)) {
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HasTBM = true;
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ToggleFeature(X86::FeatureTBM);
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}
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}
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}
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void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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@ -426,54 +191,23 @@ void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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std::string CPUName = CPU;
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if (!FS.empty() || !CPU.empty()) {
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if (CPUName.empty()) {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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if (CPUName.empty())
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CPUName = "generic";
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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}
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// If feature string is not empty, parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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} else {
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if (CPUName.empty()) {
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#if defined (__x86_64__) || defined(__i386__)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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// Make sure 64-bit features are available in 64-bit mode.
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if (In64BitMode) {
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if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
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if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
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if (X86SSELevel < SSE2) {
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X86SSELevel = SSE2;
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ToggleFeature(X86::FeatureSSE1);
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ToggleFeature(X86::FeatureSSE2);
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}
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}
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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}
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// CPUName may have been set by the CPU detection code. Make sure the
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// new MCSchedModel is used.
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// If feature string is not empty, parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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// Make sure the right MCSchedModel is used.
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InitCPUSchedModel(CPUName);
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if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
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@ -235,10 +235,6 @@ public:
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
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/// instruction.
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void AutoDetectSubtargetFeatures();
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/// \brief Reset the features for the X86 target.
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void resetSubtargetFeatures(const MachineFunction *MF) override;
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private:
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