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expose commutativity information
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23498 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -81,27 +81,36 @@ def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
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SDTCisVTSmallerThanOp<2, 1>
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]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Properties.
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//
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// Note: These are hard coded into tblgen.
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//
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class SDNodeProperty;
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def SDNPCommutative : SDNodeProperty;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node definitions.
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//
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class SDNode<string opcode, SDTypeProfile typeprof, string sdclass = "SDNode"> {
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class SDNode<string opcode, SDTypeProfile typeprof,
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list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
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string Opcode = opcode;
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string SDClass = sdclass;
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list<SDNodeProperty> Properties = props;
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SDTypeProfile TypeProfile = typeprof;
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}
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def set;
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def node;
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def imm : SDNode<"ISD::Constant" , SDTImm , "ConstantSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTVT , "VTSDNode">;
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def and : SDNode<"ISD::AND" , SDTIntBinOp>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp>;
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def xor : SDNode<"ISD::XOR" , SDTIntBinOp>;
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def add : SDNode<"ISD::ADD" , SDTBinOp>;
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def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
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def and : SDNode<"ISD::AND" , SDTIntBinOp, [SDNPCommutative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp, [SDNPCommutative]>;
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def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative]>;
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def add : SDNode<"ISD::ADD" , SDTBinOp , [SDNPCommutative]>;
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def sub : SDNode<"ISD::SUB" , SDTBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTBinOp , [SDNPCommutative]>;
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def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp>;
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