RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-09 05:57:23 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix mmx paddq, add support for the 'y' register class, though it isn't tested.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35940 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-04-12 04:14:49 +00:00
parent 4e3e115e15
commit 6c284d716e
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -321,6 +321,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::ADD, MVT::v8i8, Legal);
setOperationAction(ISD::ADD, MVT::v4i16, Legal);
setOperationAction(ISD::ADD, MVT::v2i32, Legal);
setOperationAction(ISD::ADD, MVT::v1i64, Legal);
setOperationAction(ISD::SUB, MVT::v8i8, Legal);
setOperationAction(ISD::SUB, MVT::v4i16, Legal);
@ -4636,7 +4637,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
else if (VT == MVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
break;
// FIXME: not handling MMX registers yet ('y' constraint).
case 'y': // MMX_REGS if MMX allowed.
if (!Subtarget->hasMMX()) break;
return std::make_pair(0U, X86::VR64RegisterClass);
break;
case 'Y': // SSE_REGS if SSE2 allowed
if (!Subtarget->hasSSE2()) break;
// FALL THROUGH.