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Don't use MachineOperator::is(Phys|Virt)Register

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-10 20:31:28 +00:00
parent b2e5db94cf
commit 6d21518718
3 changed files with 4 additions and 4 deletions
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2
lib/Target/X86/FloatingPoint.cpp
View File

@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
}
static unsigned getFPReg(const MachineOperand &MO) {
assert(MO.isPhysicalRegister() && "Expected an FP register!");
assert(MO.isRegister() && "Expected an FP register!");
unsigned Reg = MO.getReg();
assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
return Reg - X86::FP0;

2
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
}
static unsigned getFPReg(const MachineOperand &MO) {
assert(MO.isPhysicalRegister() && "Expected an FP register!");
assert(MO.isRegister() && "Expected an FP register!");
unsigned Reg = MO.getReg();
assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
return Reg - X86::FP0;

4
lib/Target/X86/X86InstrInfo.cpp
View File

@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
// Make sure the instruction is EXACTLY `xchg ax, ax'
if (MI.getOpcode() == X86::XCHGrr16) {
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
if (op0.isPhysicalRegister() && op0.getReg() == X86::AX &&
op1.isPhysicalRegister() && op1.getReg() == X86::AX) {
if (op0.isRegister() && op0.getReg() == X86::AX &&
op1.isRegister() && op1.getReg() == X86::AX) {
return true;
}
}