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Revert r146997, "Heed spill slot alignment on ARM."

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This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-01-03 22:34:35 +00:00
parent 2d44e02533
commit 6d5b7cc235
4 changed files with 6 additions and 6 deletions
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5
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -765,8 +765,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break;
case 16:
if (ARM::QPRRegClass.hasSubClassEq(RC)) {
// Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
.addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
@ -915,7 +914,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break;
case 16:
if (ARM::QPRRegClass.hasSubClassEq(RC)) {
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
.addFrameIndex(FI).addImm(16)
.addMemOperand(MMO));

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -542,7 +542,7 @@ needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
F->hasFnAttr(Attribute::StackAlignment));
return requiresRealignment && canRealignStack(MF);

3
test/CodeGen/ARM/fast-isel-deadcode.ll
View File

@ -15,7 +15,8 @@ entry:
; THUMB-NOT: sxtb
; THUMB: movs r0, #0
; THUMB: movt r0, #0
; THUMB: pop
; THUMB: add sp, #32
; THUMb: pop {r7, pc}
ret i32 0
}

2
test/CodeGen/Thumb2/aligned-spill.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
; DONT: llc < %s -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills | FileCheck %s --check-prefix=NEON
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios"