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New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace

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hasInFlag, hasOutFlag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-01-09 18:28:21 +00:00
parent 51fecc80f7
commit 6da8d99f70
8 changed files with 23 additions and 39 deletions
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14
lib/Target/PowerPC/PPCInstrInfo.td
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@ -47,7 +47,8 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain]>;
def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// PowerPC specific transformation functions and pattern fragments.
@ -222,13 +223,10 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
}
let isTerminator = 1 in {
let isTerminator = 1, noResults = 1 in {
// FIXME: temporary workaround for return without an incoming flag.
let isReturn = 1, noResults = 1 in
def BLRVOID : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(ret)]>;
let isReturn = 1, noResults = 1, hasInFlag = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, []>;
let noResults = 1 in
let isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
}
@ -1072,8 +1070,6 @@ def : Pat<(v4i32 (load xoaddr:$src)),
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(retflag), (BLR)>;
// Same as above, but using a temporary. FIXME: implement temporaries :)
/*
def : Pattern<(xor GPRC:$in, imm:$imm),

3
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@ -373,8 +373,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;
// FIXME: BLRVOID should be removed. See PPCInstrInfo.td
assert((MBBI->getOpcode() == PPC::BLR || MBBI->getOpcode() == PPC::BLRVOID) &&
assert(MBBI->getOpcode() == PPC::BLR &&
"Can only insert epilog into returning blocks");
// Get the number of bytes allocated from the FrameInfo...

17
lib/Target/Sparc/SparcInstrInfo.td
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@ -94,10 +94,12 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
def call : SDNode<"ISD::CALL", SDT_V8Call,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// Instructions
@ -173,10 +175,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
// FIXME: temporary workaround for return without an incoming flag.
def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
let hasInFlag = 1 in
def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
}
// Section B.1 - Load Integer Instructions, p. 90
@ -563,7 +562,7 @@ def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1,
hasDelaySlot = 1, isCall = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstV8<(ops calltarget:$dst),
@ -725,10 +724,6 @@ def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
// Return of a value, which has an input flag.
def : Pat<(retflag), (RETL)>;
// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;

3
lib/Target/Sparc/SparcRegisterInfo.cpp
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@ -165,8 +165,7 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
assert(MBBI->getOpcode() == V8::RETL &&
"Can only put epilog before 'retl' instruction!");
BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
}

17
lib/Target/SparcV8/SparcV8InstrInfo.td
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@ -94,10 +94,12 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
def call : SDNode<"ISD::CALL", SDT_V8Call,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// Instructions
@ -173,10 +175,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
// FIXME: temporary workaround for return without an incoming flag.
def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
let hasInFlag = 1 in
def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
}
// Section B.1 - Load Integer Instructions, p. 90
@ -563,7 +562,7 @@ def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1,
hasDelaySlot = 1, isCall = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstV8<(ops calltarget:$dst),
@ -725,10 +724,6 @@ def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
// Return of a value, which has an input flag.
def : Pat<(retflag), (RETL)>;
// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;

3
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
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@ -165,8 +165,7 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
assert(MBBI->getOpcode() == V8::RETL &&
"Can only put epilog before 'retl' instruction!");
BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
}

2
lib/Target/Target.td
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@ -169,8 +169,6 @@ class Instruction {
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit hasInFlag = 0; // Does this instruction read a flag operand?
bit hasOutFlag = 0; // Does this instruction write a flag operand?
bit noResults = 0; // Does this instruction produce no results?
InstrItinClass Itinerary; // Execution steps used for scheduling.

3
lib/Target/TargetSelectionDAG.td
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@ -174,6 +174,9 @@ class SDNodeProperty;
def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
def SDNPOutFlag : SDNodeProperty; // Write a flag result
def SDNPInFlag : SDNodeProperty; // Read a flag operand
def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.