From 6dcccf4d12d63fb854c46924f076871023ef7216 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Wed, 12 Oct 2016 22:53:41 +0000
Subject: [PATCH] Handle lane masks in LivePhysRegs when adding live-ins

Differential Revision: https://reviews.llvm.org/D25533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284076 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/LivePhysRegs.h           |  5 +++
 lib/CodeGen/LivePhysRegs.cpp                  | 17 +++++---
 .../Hexagon/livephysregs-lane-masks.mir       | 40 +++++++++++++++++++
 3 files changed, 57 insertions(+), 5 deletions(-)
 create mode 100644 test/CodeGen/Hexagon/livephysregs-lane-masks.mir

diff --git a/include/llvm/CodeGen/LivePhysRegs.h b/include/llvm/CodeGen/LivePhysRegs.h
index 1cea9d5b90d..d5be01012c2 100644
--- a/include/llvm/CodeGen/LivePhysRegs.h
+++ b/include/llvm/CodeGen/LivePhysRegs.h
@@ -141,6 +141,11 @@ public:
 
   /// \brief Dumps the currently live registers to the debug output.
   void dump() const;
+
+private:
+  /// Adds live-in registers from basic block @p MBB, taking associated
+  /// lane masks into consideration.
+  void addBlockLiveIns(const MachineBasicBlock &MBB);
 };
 
 inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) {
diff --git a/lib/CodeGen/LivePhysRegs.cpp b/lib/CodeGen/LivePhysRegs.cpp
index 78632873642..7d0bf743f31 100644
--- a/lib/CodeGen/LivePhysRegs.cpp
+++ b/lib/CodeGen/LivePhysRegs.cpp
@@ -141,9 +141,16 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
 }
 
 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
-static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
-  for (const auto &LI : MBB.liveins())
-    LiveRegs.addReg(LI.PhysReg);
+void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
+  for (const auto &LI : MBB.liveins()) {
+    if (LI.LaneMask == ~0u) {
+      addReg(LI.PhysReg);
+      continue;
+    }
+    for (MCSubRegIndexIterator S(LI.PhysReg, TRI); S.isValid(); ++S)
+      if (LI.LaneMask & TRI->getSubRegIndexLaneMask(S.getSubRegIndex()))
+        addReg(S.getSubReg());
+  }
 }
 
 /// Add pristine registers to the given \p LiveRegs. This function removes
@@ -160,7 +167,7 @@ static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF,
 void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
   // To get the live-outs we simply merge the live-ins of all successors.
   for (const MachineBasicBlock *Succ : MBB.successors())
-    ::addLiveIns(*this, *Succ);
+    addBlockLiveIns(*Succ);
 }
 
 void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
@@ -185,5 +192,5 @@ void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   if (MFI.isCalleeSavedInfoValid())
     addPristines(*this, MF, MFI, *TRI);
-  ::addLiveIns(*this, MBB);
+  addBlockLiveIns(MBB);
 }
diff --git a/test/CodeGen/Hexagon/livephysregs-lane-masks.mir b/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
new file mode 100644
index 00000000000..b2e1968bb59
--- /dev/null
+++ b/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
@@ -0,0 +1,40 @@
+# RUN: llc -march=hexagon -run-pass if-converter -verify-machineinstrs -o - %s | FileCheck %s
+
+# CHECK-LABEL: name: foo
+# CHECK: %p0 = C2_cmpeqi %r16, 0
+# Make sure there is no implicit use of r1.
+# CHECK: %r1 = L2_ploadruhf_io %p0, %r29, 6
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+
+---
+name: foo
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %r16
+    successors: %bb.1, %bb.2
+        %p0 = C2_cmpeqi %r16, 0
+        J2_jumpt %p0, %bb.2, implicit-def %pc
+
+  bb.1:
+    ; The lane mask %d0:0002 is equivalent to %r0. LivePhysRegs would ignore
+    ; it and treat it as the whole %d0, which is a pair %r1, %r0. The extra
+    ; %r1 would cause an (undefined) implicit use to be added during
+    ; if-conversion.
+    liveins: %d0:0x00000002, %d15:0x00000001, %r16
+    successors: %bb.2
+        %r1 = L2_loadruh_io %r29, 6
+        S2_storeri_io killed %r16, 0, %r1
+
+  bb.2:
+    liveins: %r0
+        %d8 = L2_loadrd_io %r29, 8
+        L4_return implicit-def %r29, implicit-def %r30, implicit-def %r31, implicit-def %pc, implicit %r30
+