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[ms-inline asm] Use the new API introduced in r165830 in lieu of the

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MapAndConstraints vector.  Also remove the unused Kind argument.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-10-12 22:53:36 +00:00
parent 0d218994f1
commit 6e006d3de8
6 changed files with 36 additions and 70 deletions
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14
include/llvm/MC/MCTargetAsmParser.h
View File

@ -50,12 +50,6 @@ public:
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) = 0;
/// MapAndConstraints - Map inline assembly operands to MCInst operands
/// and an associated constraint.
typedef std::pair< unsigned, std::string > MapAndConstraint;
typedef SmallVector<MapAndConstraint, 4> MatchInstMapAndConstraints;
typedef SmallVectorImpl<MapAndConstraint> MatchInstMapAndConstraintsImpl;
/// ParseInstruction - Parse one assembly instruction.
///
/// The parser is positioned following the instruction name. The target
@ -97,9 +91,8 @@ public:
virtual bool
MatchInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
MatchInstMapAndConstraintsImpl &MapAndConstraints,
unsigned &OrigErrorInfo, bool matchingInlineAsm = false) {
MCStreamer &Out, unsigned &Opcode, unsigned &OrigErrorInfo,
bool matchingInlineAsm = false) {
OrigErrorInfo = ~0x0;
return true;
}
@ -122,8 +115,7 @@ public:
}
virtual void convertToMapAndConstraints(unsigned Kind,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MatchInstMapAndConstraintsImpl &MapAndConstraints) = 0;
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
};
} // End llvm namespace

5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -7478,12 +7478,9 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned ErrorInfo;
unsigned MatchResult;
MatchInstMapAndConstraints MapAndConstraints;
MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
MapAndConstraints, ErrorInfo,
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
/*matchingInlineAsm*/ false);
switch (MatchResult) {
default: break;

6
lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
View File

@ -316,11 +316,9 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned ErrorInfo;
MatchInstMapAndConstraints MapAndConstraints;
switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints,
ErrorInfo, /*matchingInlineAsm*/ false)) {
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo,
/*matchingInlineAsm*/ false)) {
default: break;
case Match_Success:
Out.EmitInstruction(Inst);

5
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -456,11 +456,8 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned ErrorInfo;
MatchInstMapAndConstraints MapAndConstraints;
unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
MapAndConstraints, ErrorInfo,
unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
/*matchingInlineAsm*/ false);
switch (MatchResult) {

39
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -68,9 +68,8 @@ private:
MCStreamer &Out);
bool MatchInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
MatchInstMapAndConstraintsImpl &MapAndConstraints,
unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
MCStreamer &Out, unsigned &Opcode,
unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
/// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
/// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
@ -1523,21 +1522,17 @@ bool X86AsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
MatchInstMapAndConstraints MapAndConstraints;
bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode,
MapAndConstraints, ErrorInfo);
bool Error = MatchInstruction(IDLoc, Operands, Out, Opcode, ErrorInfo);
return Error;
}
bool X86AsmParser::
MatchInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,
unsigned &OrigErrorInfo, bool matchingInlineAsm) {
MCStreamer &Out, unsigned &Opcode, unsigned &OrigErrorInfo,
bool matchingInlineAsm) {
assert(!Operands.empty() && "Unexpect empty operand list!");
X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
assert(Op->isToken() && "Leading operand should always be a mnemonic!");
@ -1577,7 +1572,7 @@ MatchInstruction(SMLoc IDLoc,
MCInst Inst;
// First, try a direct match.
switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints,
switch (MatchInstructionImpl(Operands, Inst,
OrigErrorInfo, matchingInlineAsm,
isParsingIntelSyntax())) {
default: break;
@ -1629,24 +1624,18 @@ MatchInstruction(SMLoc IDLoc,
Tmp[Base.size()] = Suffixes[0];
unsigned ErrorInfoIgnore;
unsigned Match1, Match2, Match3, Match4;
unsigned tKind;
MatchInstMapAndConstraints tMapAndConstraints[4];
Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0],
ErrorInfoIgnore, isParsingIntelSyntax());
if (Match1 == Match_Success) Kind = tKind;
Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
isParsingIntelSyntax());
Tmp[Base.size()] = Suffixes[1];
Match2 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[1],
ErrorInfoIgnore, isParsingIntelSyntax());
if (Match2 == Match_Success) Kind = tKind;
Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
isParsingIntelSyntax());
Tmp[Base.size()] = Suffixes[2];
Match3 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[2],
ErrorInfoIgnore, isParsingIntelSyntax());
if (Match3 == Match_Success) Kind = tKind;
Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
isParsingIntelSyntax());
Tmp[Base.size()] = Suffixes[3];
Match4 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[3],
ErrorInfoIgnore, isParsingIntelSyntax());
if (Match4 == Match_Success) Kind = tKind;
Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
isParsingIntelSyntax());
// Restore the old token.
Op->setTokenValue(Base);

37
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -1714,9 +1714,7 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
OpOS << "void " << Target.getName() << ClassName << "::\n"
<< "convertToMapAndConstraints(unsigned Kind,\n";
OpOS.indent(27);
OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
OpOS.indent(27);
OpOS << "MatchInstMapAndConstraintsImpl &MapAndConstraints) {\n"
OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
<< " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
<< " unsigned NumMCOperands = 0;\n"
<< " const uint8_t *Converter = ConversionTable[Kind];\n"
@ -1724,9 +1722,11 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
<< " switch (*p) {\n"
<< " default: llvm_unreachable(\"invalid conversion entry!\");\n"
<< " case CVT_Reg:\n"
<< " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
<< " Operands[*(p + 1)]->setConstraint(\"m\");\n"
<< " ++NumMCOperands;\n"
<< " break;\n"
<< " case CVT_Tied:\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands,"
<< "\"m\"));\n"
<< " ++NumMCOperands;\n"
<< " break;\n";
@ -1823,8 +1823,8 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
// Add a handler for the operand number lookup.
OpOS << " case " << Name << ":\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
<< ",\"m\"));\n"
<< " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
<< " Operands[*(p + 1)]->setConstraint(\"m\");\n"
<< " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
<< " break;\n";
break;
@ -1862,8 +1862,8 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
<< " break;\n";
OpOS << " case " << Name << ":\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
<< ",\"\"));\n"
<< " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
<< " Operands[*(p + 1)]->setConstraint(\"\");\n"
<< " ++NumMCOperands;\n"
<< " break;\n";
break;
@ -1893,8 +1893,8 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
<< " break;\n";
OpOS << " case " << Name << ":\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
<< ",\"m\"));\n"
<< " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
<< " Operands[*(p + 1)]->setConstraint(\"m\");\n"
<< " ++NumMCOperands;\n"
<< " break;\n";
}
@ -2604,16 +2604,12 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< " const SmallVectorImpl<MCParsedAsmOperand*> "
<< "&Operands);\n";
OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
OS.indent(29);
OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints);\n";
OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
OS << " bool mnemonicIsValid(StringRef Mnemonic);\n";
OS << " unsigned MatchInstructionImpl(\n";
OS.indent(27);
OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
<< " unsigned &Kind, MCInst &Inst,\n";
OS.indent(30);
OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints,\n"
<< " MCInst &Inst,\n"
<< " unsigned &ErrorInfo,"
<< " bool matchingInlineAsm,\n"
<< " unsigned VariantID = 0);\n";
@ -2806,8 +2802,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< Target.getName() << ClassName << "::\n"
<< "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
<< " &Operands,\n";
OS << " unsigned &Kind, MCInst &Inst,\n"
<< "SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,\n"
OS << " MCInst &Inst,\n"
<< "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
OS << " // Eliminate obvious mismatches.\n";
@ -2903,10 +2898,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " }\n";
OS << "\n";
OS << " if (matchingInlineAsm) {\n";
OS << " Kind = it->ConvertFn;\n";
OS << " Inst.setOpcode(it->Opcode);\n";
OS << " convertToMapAndConstraints(it->ConvertFn, Operands, "
<< "MapAndConstraints);\n";
OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
OS << " return Match_Success;\n";
OS << " }\n\n";
OS << " // We have selected a definite instruction, convert the parsed\n"