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Fixed spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8588 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
a589d31faa
commit
6eba07a6a3
@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
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return false;
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// Finally, if the instruction preceeds the branch, we make sure the
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// Finally, if the instruction precedes the branch, we make sure the
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// instruction can be reordered relative to the branch. We simply check
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// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
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//
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@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
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bool nodeIsPredecessor)
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{
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if (nodeIsPredecessor) {
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// If node is in the same basic block (i.e., preceeds brNode),
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// If node is in the same basic block (i.e., precedes brNode),
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// remove it and all its incident edges from the graph. Make sure we
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// add dummy edges for pred/succ nodes that become entry/exit nodes.
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graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
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@ -4,7 +4,7 @@
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// tree if one or more of them might be potentially combined into a single
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// complex instruction in the target machine.
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// Since this grouping is completely machine-independent, we do it as
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// aggressive as possible to exploit any possible taret instructions.
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// aggressive as possible to exploit any possible target instructions.
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// In particular, we group two instructions O and I if:
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// (1) Instruction O computes an operand used by instruction I,
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// and (2) O and I are part of the same basic block,
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@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
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{
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mcfi.addTemp(this);
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Operands.push_back(Use(s1, this)); // s1 must be nonnull
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Operands.push_back(Use(s1, this)); // s1 must be non-null
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if (s2) {
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Operands.push_back(Use(s2, this));
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}
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@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
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MachineFunction &MF = MachineFunction::get(BB->getParent());
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// FIXME: if PHI instructions existed in the machine code, this would be
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// unnecesary.
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// unnecessary.
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MachineBasicBlock *MBB = 0;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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if (I->getBasicBlock() == BB) {
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@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
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}
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}
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// Finally, do any postprocessing on this node after its children
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// Finally, do any post-processing on this node after its children
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// have been translated
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//
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if (treeRoot->opLabel != VRegListOp)
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@ -127,7 +127,7 @@ MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
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}
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// Subsitute all occurrences of Value* oldVal with newVal in all operands
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// Substitute all occurrences of Value* oldVal with newVal in all operands
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// and all implicit refs.
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// If defsOnly == true, substitute defs only.
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unsigned
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@ -140,7 +140,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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unsigned numSubst = 0;
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// Subsitute operands
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// Substitute operands
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for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
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if (*O == oldVal)
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if (!defsOnly ||
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@ -153,7 +153,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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else
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someArgsWereIgnored = true;
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// Subsitute implicit refs
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// Substitute implicit refs
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for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
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if (getImplicitRef(i) == oldVal)
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if (!defsOnly ||
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@ -301,7 +301,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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OS << "<def>";
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}
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// code for printing implict references
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// code for printing implicit references
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if (getNumImplicitRefs()) {
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OS << "\tImplicitRefs: ";
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for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
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@ -330,7 +330,7 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
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os << "<d&u>";
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}
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// code for printing implict references
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// code for printing implicit references
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unsigned NumOfImpRefs = MI.getNumImplicitRefs();
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if (NumOfImpRefs > 0) {
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os << "\tImplicit: ";
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@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
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return false;
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// Finally, if the instruction preceeds the branch, we make sure the
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// Finally, if the instruction precedes the branch, we make sure the
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// instruction can be reordered relative to the branch. We simply check
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// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
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//
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@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
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bool nodeIsPredecessor)
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{
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if (nodeIsPredecessor) {
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// If node is in the same basic block (i.e., preceeds brNode),
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// If node is in the same basic block (i.e., precedes brNode),
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// remove it and all its incident edges from the graph. Make sure we
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// add dummy edges for pred/succ nodes that become entry/exit nodes.
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graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
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@ -4,7 +4,7 @@
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// tree if one or more of them might be potentially combined into a single
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// complex instruction in the target machine.
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// Since this grouping is completely machine-independent, we do it as
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// aggressive as possible to exploit any possible taret instructions.
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// aggressive as possible to exploit any possible target instructions.
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// In particular, we group two instructions O and I if:
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// (1) Instruction O computes an operand used by instruction I,
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// and (2) O and I are part of the same basic block,
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@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
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{
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mcfi.addTemp(this);
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Operands.push_back(Use(s1, this)); // s1 must be nonnull
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Operands.push_back(Use(s1, this)); // s1 must be non-null
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if (s2) {
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Operands.push_back(Use(s2, this));
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}
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@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
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MachineFunction &MF = MachineFunction::get(BB->getParent());
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// FIXME: if PHI instructions existed in the machine code, this would be
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// unnecesary.
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// unnecessary.
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MachineBasicBlock *MBB = 0;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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if (I->getBasicBlock() == BB) {
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@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
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}
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}
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// Finally, do any postprocessing on this node after its children
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// Finally, do any post-processing on this node after its children
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// have been translated
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//
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if (treeRoot->opLabel != VRegListOp)
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