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ARM: Fix cmpxchg O0 expansion
This is the equivalent of r304048 for ARM:
- Rewrite livein calculation to use the computeLiveIns() helper
function. This is slightly less efficient but easier to reason about
and doesn't unnecessarily add pristine and reserved registers[1]
- Zero the status register at the beginning of the loop to make sure it
has a defined value.
- Remove kill flags of values that need to stay alive throughout the loop.
[1] An upcoming commit of mine will tighten the MachineVerifier to catch
these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
parent
5cc8b8253e
commit
6ef5e10ad7
@ -757,14 +757,9 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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MI.eraseFromParent();
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}
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static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs) {
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for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
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MBB->addLiveIn(*I);
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}
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/// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
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/// possible. This only gets used at -O0 so we don't care about efficiency of the
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/// generated code.
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/// possible. This only gets used at -O0 so we don't care about efficiency of
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/// the generated code.
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bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned LdrexOp, unsigned StrexOp,
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@ -773,16 +768,15 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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bool IsThumb = STI->isThumb();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineOperand &Dest = MI.getOperand(0);
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const MachineOperand &Dest = MI.getOperand(0);
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unsigned StatusReg = MI.getOperand(1).getReg();
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MachineOperand &Addr = MI.getOperand(2);
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MachineOperand &Desired = MI.getOperand(3);
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MachineOperand &New = MI.getOperand(4);
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LivePhysRegs LiveRegs(TII->getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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for (auto I = std::prev(MBB.end()); I != MBBI; --I)
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LiveRegs.stepBackward(*I);
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bool StatusDead = MI.getOperand(1).isDead();
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// Duplicating undef operands into 2 instructions does not guarantee the same
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// value on both; However undef should be replaced by xzr anyway.
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assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
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unsigned AddrReg = MI.getOperand(2).getReg();
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unsigned DesiredReg = MI.getOperand(3).getReg();
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unsigned NewReg = MI.getOperand(4).getReg();
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MachineFunction *MF = MBB.getParent();
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auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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@ -795,25 +789,35 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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if (UxtOp) {
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, DL, TII->get(UxtOp), Desired.getReg())
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.addReg(Desired.getReg(), RegState::Kill);
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BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
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.addReg(DesiredReg, RegState::Kill);
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if (!IsThumb)
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MIB.addImm(0);
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MIB.add(predOps(ARMCC::AL));
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}
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// .Lloadcmp:
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// mov wStatus, #0
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// ldrex rDest, [rAddr]
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// cmp rDest, rDesired
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// bne .Ldone
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LoadCmpBB->addLiveIn(Addr.getReg());
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LoadCmpBB->addLiveIn(Dest.getReg());
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LoadCmpBB->addLiveIn(Desired.getReg());
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addPostLoopLiveIns(LoadCmpBB, LiveRegs);
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if (!StatusDead) {
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if (IsThumb) {
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BuildMI(LoadCmpBB, DL, TII->get(ARM::tMOVi8), StatusReg)
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.addDef(ARM::CPSR, RegState::Dead)
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.addImm(0)
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.add(predOps(ARMCC::AL));
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} else {
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BuildMI(LoadCmpBB, DL, TII->get(ARM::MOVi), StatusReg)
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.addImm(0)
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.add(predOps(ARMCC::AL))
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.add(condCodeOp());
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}
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}
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MachineInstrBuilder MIB;
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MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
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MIB.addReg(Addr.getReg());
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MIB.addReg(AddrReg);
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if (LdrexOp == ARM::t2LDREX)
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MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
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MIB.add(predOps(ARMCC::AL));
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@ -821,7 +825,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
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BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
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.addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
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.add(Desired)
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.addReg(DesiredReg)
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.add(predOps(ARMCC::AL));
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unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
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BuildMI(LoadCmpBB, DL, TII->get(Bcc))
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@ -835,21 +839,16 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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// strex rStatus, rNew, [rAddr]
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// cmp rStatus, #0
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// bne .Lloadcmp
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StoreBB->addLiveIn(Addr.getReg());
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StoreBB->addLiveIn(New.getReg());
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addPostLoopLiveIns(StoreBB, LiveRegs);
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MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg);
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MIB.add(New);
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MIB.add(Addr);
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MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg)
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.addReg(NewReg)
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.addReg(AddrReg);
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if (StrexOp == ARM::t2STREX)
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MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
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MIB.add(predOps(ARMCC::AL));
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unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
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BuildMI(StoreBB, DL, TII->get(CMPri))
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.addReg(StatusReg, RegState::Kill)
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.addReg(StatusReg, getKillRegState(StatusDead))
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.addImm(0)
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.add(predOps(ARMCC::AL));
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BuildMI(StoreBB, DL, TII->get(Bcc))
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@ -861,12 +860,24 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
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DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
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DoneBB->transferSuccessors(&MBB);
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addPostLoopLiveIns(DoneBB, LiveRegs);
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MBB.addSuccessor(LoadCmpBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Recompute livein lists.
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const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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LivePhysRegs LiveRegs;
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computeLiveIns(LiveRegs, MRI, *DoneBB);
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computeLiveIns(LiveRegs, MRI, *StoreBB);
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computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
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// Do an extra pass around the loop to get loop carried registers right.
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StoreBB->clearLiveIns();
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computeLiveIns(LiveRegs, MRI, *StoreBB);
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LoadCmpBB->clearLiveIns();
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computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
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return true;
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}
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@ -894,19 +905,19 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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DebugLoc DL = MI.getDebugLoc();
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MachineOperand &Dest = MI.getOperand(0);
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unsigned StatusReg = MI.getOperand(1).getReg();
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MachineOperand &Addr = MI.getOperand(2);
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MachineOperand &Desired = MI.getOperand(3);
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MachineOperand &New = MI.getOperand(4);
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bool StatusDead = MI.getOperand(1).isDead();
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// Duplicating undef operands into 2 instructions does not guarantee the same
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// value on both; However undef should be replaced by xzr anyway.
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assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
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unsigned AddrReg = MI.getOperand(2).getReg();
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unsigned DesiredReg = MI.getOperand(3).getReg();
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MachineOperand New = MI.getOperand(4);
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New.setIsKill(false);
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unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
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unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
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unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0);
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unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
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LivePhysRegs LiveRegs(TII->getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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for (auto I = std::prev(MBB.end()); I != MBBI; --I)
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LiveRegs.stepBackward(*I);
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unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
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unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
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MachineFunction *MF = MBB.getParent();
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auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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@ -922,26 +933,21 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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// cmp rDestLo, rDesiredLo
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// sbcs rStatus<dead>, rDestHi, rDesiredHi
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// bne .Ldone
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LoadCmpBB->addLiveIn(Addr.getReg());
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LoadCmpBB->addLiveIn(Dest.getReg());
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LoadCmpBB->addLiveIn(Desired.getReg());
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addPostLoopLiveIns(LoadCmpBB, LiveRegs);
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unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
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MachineInstrBuilder MIB;
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MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
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addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
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MIB.addReg(Addr.getReg()).add(predOps(ARMCC::AL));
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MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
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unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
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BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
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.addReg(DestLo, getKillRegState(Dest.isDead()))
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.addReg(DesiredLo, getKillRegState(Desired.isDead()))
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.addReg(DesiredLo)
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.add(predOps(ARMCC::AL));
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BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
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.addReg(DestHi, getKillRegState(Dest.isDead()))
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.addReg(DesiredHi, getKillRegState(Desired.isDead()))
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.addReg(DesiredHi)
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.addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
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unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
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@ -956,18 +962,14 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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// strexd rStatus, rNewLo, rNewHi, [rAddr]
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// cmp rStatus, #0
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// bne .Lloadcmp
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StoreBB->addLiveIn(Addr.getReg());
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StoreBB->addLiveIn(New.getReg());
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addPostLoopLiveIns(StoreBB, LiveRegs);
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unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
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MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg);
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addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
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MIB.add(Addr).add(predOps(ARMCC::AL));
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MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
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unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
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BuildMI(StoreBB, DL, TII->get(CMPri))
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.addReg(StatusReg, RegState::Kill)
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.addReg(StatusReg, getKillRegState(StatusDead))
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.addImm(0)
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.add(predOps(ARMCC::AL));
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BuildMI(StoreBB, DL, TII->get(Bcc))
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@ -979,12 +981,24 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
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DoneBB->transferSuccessors(&MBB);
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addPostLoopLiveIns(DoneBB, LiveRegs);
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MBB.addSuccessor(LoadCmpBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Recompute livein lists.
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const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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LivePhysRegs LiveRegs;
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computeLiveIns(LiveRegs, MRI, *DoneBB);
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computeLiveIns(LiveRegs, MRI, *StoreBB);
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computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
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// Do an extra pass around the loop to get loop carried registers right.
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StoreBB->clearLiveIns();
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computeLiveIns(LiveRegs, MRI, *StoreBB);
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LoadCmpBB->clearLiveIns();
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computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
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return true;
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}
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@ -10,10 +10,11 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
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; CHECK: dmb ish
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; CHECK: uxtb [[DESIRED:r[0-9]+]], [[DESIRED]]
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: mov{{s?}} [[STATUS:r[0-9]+]], #0
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; CHECK: ldrexb [[OLD:r[0-9]+]], [r0]
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; CHECK: cmp [[OLD]], [[DESIRED]]
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; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: strexb [[STATUS:r[0-9]+]], r2, [r0]
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; CHECK: strexb [[STATUS]], r2, [r0]
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; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
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; CHECK: bne [[RETRY]]
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; CHECK: [[DONE]]:
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@ -29,10 +30,11 @@ define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind
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; CHECK: dmb ish
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; CHECK: uxth [[DESIRED:r[0-9]+]], [[DESIRED]]
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: mov{{s?}} [[STATUS:r[0-9]+]], #0
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; CHECK: ldrexh [[OLD:r[0-9]+]], [r0]
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; CHECK: cmp [[OLD]], [[DESIRED]]
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; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: strexh [[STATUS:r[0-9]+]], r2, [r0]
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; CHECK: strexh [[STATUS]], r2, [r0]
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; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
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; CHECK: bne [[RETRY]]
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; CHECK: [[DONE]]:
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@ -48,10 +50,11 @@ define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind
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; CHECK: dmb ish
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; CHECK-NOT: uxt
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: mov{{s?}} [[STATUS:r[0-9]+]], #0
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; CHECK: ldrex [[OLD:r[0-9]+]], [r0]
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; CHECK: cmp [[OLD]], [[DESIRED]]
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; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: strex [[STATUS:r[0-9]+]], r2, [r0]
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; CHECK: strex [[STATUS]], r2, [r0]
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; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
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; CHECK: bne [[RETRY]]
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; CHECK: [[DONE]]:
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