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Add -sse[,2,3] arguments to LLC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16018 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-24 08:18:44 +00:00
parent 47d2f2bb50
commit 6f0161aac3
2 changed files with 20 additions and 0 deletions
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6
lib/Target/X86/X86.h
View File

@ -23,6 +23,12 @@ class TargetMachine;
class FunctionPass;
class IntrinsicLowering;
enum X86VectorEnum {
NoSSE, SSE, SSE2, SSE3
};
extern X86VectorEnum X86Vector;
/// createX86SimpleInstructionSelector - This pass converts an LLVM function
/// into a machine code representation in a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple.

14
lib/Target/X86/X86TargetMachine.cpp
View File

@ -25,6 +25,8 @@
#include "Support/Statistic.h"
using namespace llvm;
X86VectorEnum llvm::X86Vector = NoSSE;
namespace {
cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
cl::desc("Disable the ssa-based peephole optimizer "
@ -33,6 +35,18 @@ namespace {
cl::desc("Disable the X86 asm printer, for use "
"when profiling the code generator."));
// FIXME: This should eventually be handled with target triples and
// subtarget support!
cl::opt<X86VectorEnum, true>
SSEArg(
cl::desc("Enable SSE support in the X86 target:"),
cl::values(
clEnumValN(SSE, "sse", " Enable SSE support"),
clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
clEnumValEnd),
cl::location(X86Vector), cl::init(NoSSE));
// Register the target.
RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
}